Zobrazeno 1 - 10
of 190
pro vyhledávání: '"Jiun-Lang Huang"'
Publikováno v:
2022 IEEE International Test Conference in Asia (ITC-Asia).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d441c8ca3a57094bb6be4d712a36c7c
https://doi.org/10.1109/itcasia55616.2022.00019
https://doi.org/10.1109/itcasia55616.2022.00019
Publikováno v:
Proceedings of the 2022 International Symposium on Physical Design.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::51267d4138e5a415bf5bdf6b6081a13d
https://doi.org/10.1145/3505170.3511801
https://doi.org/10.1145/3505170.3511801
Publikováno v:
2021 IEEE International Test Conference in Asia (ITC-Asia).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4ca0997f1cf139f23c3dc109b361820
https://doi.org/10.1109/itc-asia53059.2021.9808811
https://doi.org/10.1109/itc-asia53059.2021.9808811
Publikováno v:
VLSI-DAT
As the design complexity grows dramatically in modern circuit designs, 2.5D/3D chip/package/board integration has become effective for optimizing system performance and power consumption. Various 2.5D/3D technologies have been explored. Among many te
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::191f00208982b7489616ed36be5eca76
https://doi.org/10.1109/vlsi-dat52063.2021.9427350
https://doi.org/10.1109/vlsi-dat52063.2021.9427350
Publikováno v:
ICCAD
As the design complexity grows dramatically in modern circuit designs, 2.5D/3D chip/package/board integration has become a key to beat process limitation for optimizing system performance and power consumption. Among the explored technologies, the wa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::07a50833642275225d80eb3c4cbc0d99
https://doi.org/10.1145/3400302.3415767
https://doi.org/10.1145/3400302.3415767
Autor:
Kuen-Wei Yeh, Jiun-Lang Huang
Publikováno v:
ITC-Asia
Many parallel test pattern generation techniques have been proposed to speed up the test pattern generation (TPG) process. Focusing on acceleration, most of these techniques sacrifice determinism and often incur test set inflation. In this paper, a p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66bc6b0f3a9abbbf5daf1d1dff67dab8
https://doi.org/10.1109/itc-asia51099.2020.00033
https://doi.org/10.1109/itc-asia51099.2020.00033
Publikováno v:
ETS
For high-performance integrated circuits with tight timing budgets, full-scan based transition delay fault (TDF) testing is mandatory to ensure high test quality. However, the discrepancy between the scan test mode and the functional mode is problema
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f41f5e4aadd366e9985f94bb245ad64
https://doi.org/10.1109/ets48528.2020.9131591
https://doi.org/10.1109/ets48528.2020.9131591
Autor:
Jiun-Lang Huang, Ching-Yuan Chen
Publikováno v:
ATS
Software-based Self-test (SBST) has been recognized as a promising complement to scan-based structural Built-in Self-test (BIST), especially for in-field self-test applications. In response to the ever-increasing complexities of the modern CPU design
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5d3f955ac463f981100f503196898b1a
https://doi.org/10.1109/ats47505.2019.00013
https://doi.org/10.1109/ats47505.2019.00013
Publikováno v:
ITC-Asia
FPGA-based digital IC test equipment is a promising solution for low to mid-end applications. In the past, several FPGA data/timing formatters have been demonstrated to generate test waveforms at 100 MHz symbol rate and 200 ps or better resolution. I
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f55add57af5d028714565033cc5b51c7
https://doi.org/10.1109/itc-asia.2019.00018
https://doi.org/10.1109/itc-asia.2019.00018
Publikováno v:
DDECS
Reconvergence has been recognized as the main reason for ATPG backtrack. It induces not only more, but also prolonged backtracks and causes more severe performance degradation than expected. In this paper, we propose a reconvergence-aware testability
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99cb7d537ec8ba14e8b9219dd12de9d2
https://doi.org/10.1109/ddecs.2019.8724660
https://doi.org/10.1109/ddecs.2019.8724660