Zobrazeno 1 - 2
of 2
pro vyhledávání: '"Jitendra Pratap Singh Mathur"'
Publikováno v:
Journal of Electrical Engineering & Technology. 15:1405-1412
The manuscript presents the construction of a diagonally structured Parity check matrix using lower and upper (LU) decomposition for regular Quasi Cyclic-Low Density Parity Check Codes (QC-LDPC) with girth 12. This diagonally structured parity check
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9beb5de140a187755fcdde52cb85ce00
https://doi.org/10.1007/s42835-020-00394-w
https://doi.org/10.1007/s42835-020-00394-w
Publikováno v:
2017 International Conference on Inventive Computing and Informatics (ICICI).
This paper presents Bit error Rate performance Analysis of Quasi Cyclic Low Density Parity Check Codes (QC-LDPC) with girth 6 using Log Domain sum product and Simple Log Domain Sum Product Algorithm for Decoding. The approach to construct Parity Chec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::abd895e9a02b3031187238f5255970d8
https://doi.org/10.1109/icici.2017.8365366
https://doi.org/10.1109/icici.2017.8365366