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Autor:
Nobuto Ono, Hiroyuki Kobayashi, Takaaki Okumura, Jiro Iwai, Hidenari Nakashima, Takashi Sato, Masanori Hashimoto
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :808-814
With the recent advance of process technology shrinking, process parameter variation has become one of the major issues in SoC designs, especially for timing convergence. Recently, Statistical Static Timing Analysis (SSTA) has been proposed as a prom
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9b18fd663ec85b27005ff82573521491
https://doi.org/10.1093/ietfec/e90-a.4.808
https://doi.org/10.1093/ietfec/e90-a.4.808
