Zobrazeno 1 - 10
of 102
pro vyhledávání: '"Jinwook Burm"'
Autor:
Jaehyuk Lee, Junho Boo, Junsang Park, Taiji An, Heewook Shin, Youngjae Cho, Michael Choi, Jinwook Burm, Gilcho Ahn, Seunghoon Lee
Publikováno v:
Electronics Letters, Vol 59, Iss 16, Pp n/a-n/a (2023)
Abstract This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades
Externí odkaz:
https://doaj.org/article/b3acb75a487a48cc8440681e083cf736
Publikováno v:
2022 19th International SoC Design Conference (ISOCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7118e9c1963a71290d2ef179575ed74e
https://doi.org/10.1109/isocc56007.2022.10031329
https://doi.org/10.1109/isocc56007.2022.10031329
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 67:4029-4040
In this article, a digitally controlled voltage-mode buck converter with embedded transient improvement using delay line-based control techniques is presented. Two voltage-controlled delay lines (VCDL’s) are used to convert the difference between t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5a37b3a63fb669a9531d4b3a819ecb46
https://doi.org/10.1109/tcsi.2020.3012014
https://doi.org/10.1109/tcsi.2020.3012014
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:2831-2841
This article presents a novel method for frequency tracking based on an extended bang-bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The XBBPD-based structure has a frequency tracking range that completely cover
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::48a6a0273810a0238af2c0be340b91d6
https://doi.org/10.1109/jssc.2020.3005750
https://doi.org/10.1109/jssc.2020.3005750
Publikováno v:
IEEE Sensors Journal. 20:2831-2838
This paper proposes a low-power column-parallel two-step single slope Analog-to-Digital Converter (SS ADC) and voltage range tuned ramp generator for low-power CMOS Image Sensors (CIS). The proposed SS ADC has small bandwidth to drive the low power C
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d03e170bc21b09d2838ed00cc1f29ee
https://doi.org/10.1109/jsen.2019.2957043
https://doi.org/10.1109/jsen.2019.2957043
Publikováno v:
ISOCC
This paper presents a 2MS/ $s$ 12-bit SAR ADC with RC two-step scheme. The SAR ADC has trade-off between size and high-resolution specification. The capacitor array has size problem because total capacitance of capacitor array increases exponentially
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3765a2617f59856f3a9498aad936d104
https://doi.org/10.1109/isocc50952.2020.9332915
https://doi.org/10.1109/isocc50952.2020.9332915
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 65:1659-1663
A 30-MHz voltage-mode buck converter using a delay-line-based pulse-width-modulation controller is proposed in this brief. Two voltage-to-delay cells are used to convert the voltage difference to delay-time difference. A charge pump is used to charge
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b5acd00352cb8f2307d68091ebd29dd6
https://doi.org/10.1109/tcsii.2017.2764048
https://doi.org/10.1109/tcsii.2017.2764048
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 64:1117-1121
Without using bipolar transistors, serially connected inverter cells generate clock delay according to temperature. The delay is compared with a reference clock to estimate the temperature. The proposed time-to-digital converter (TDC) structure is us
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fef9e47c4983886667ef79d9353382bd
https://doi.org/10.1109/tcsii.2015.2503717
https://doi.org/10.1109/tcsii.2015.2503717
Publikováno v:
Microelectronics Journal. 67:19-24
This paper presents a digital phase-locked-loop (DPLL) based on multi-output bang-bang phase detector (MOBBPD) with reused most significant bits (MSBs) of MOBBPD. The MOBBPD can be implemented simply while achieving the merits of both time-to-digital
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a437b891b31db8fdc2b102fd535b6a7
https://doi.org/10.1016/j.mejo.2017.07.004
https://doi.org/10.1016/j.mejo.2017.07.004
Publikováno v:
IEEE Sensors Journal. 17:3001-3011
This paper presents a CMOS smart temperature sensor using a switched Vernier time-to-digital converter to achieve an energy-efficient temperature sensing. The proposed temperature sensor employs two switched ring oscillators (SROs), of which the osci
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bea16133613fc3875251b34752e535e5
https://doi.org/10.1109/jsen.2017.2686442
https://doi.org/10.1109/jsen.2017.2686442