Zobrazeno 1 - 10
of 43
pro vyhledávání: '"Jinsu Jeong"'
Autor:
Seungjoon Eom, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Seunghwan Lee, Jinsu Jeong, Rock‐Hyun Baek
Publikováno v:
Advanced Intelligent Systems, Vol 6, Iss 4, Pp n/a-n/a (2024)
Neural compact models are proposed to simplify device‐modeling processes without requiring domain expertise. However, the existing models have certain limitations. Specifically, some models are not parameterized, while others compromise accuracy an
Externí odkaz:
https://doaj.org/article/672e3f12053448a7829c5f701e2b5340
Publikováno v:
Nanomaterials, Vol 14, Iss 12, p 1006 (2024)
The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide
Externí odkaz:
https://doaj.org/article/2e659478395c457a985a4672b228dc7e
Autor:
Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Junjong Lee, Sanguk Lee, Jaewan Lim, Rock-Hyun Baek
Publikováno v:
IEEE Access, Vol 10, Pp 22032-22037 (2022)
Grain boundary (GB) at the source/drain (S/D) epitaxy was investigated using fully-calibrated TCAD. Because the S/D epi is grown separately at the bottom and the NS channels, nanosheet field-effect transistors (NSFETs) have unwanted GB within the S/D
Externí odkaz:
https://doaj.org/article/376710b9e59a43abb680aeff5772f010
Publikováno v:
IEEE Access, Vol 9, Pp 16728-16735 (2021)
Through-silicon via (TSV)-induced mechanical stress and electrical noise coupling effects on sub 5-nm node nanosheet field-effect transistors (NSFETs) were investigated comprehensively compared to fin-shaped FETs (FinFETs) using TCAD for heterogeneou
Externí odkaz:
https://doaj.org/article/acf36e80602f464ba02dcb1b8752cd32
Publikováno v:
IEEE Access, Vol 9, Pp 138192-138199 (2021)
For the first time, we suggested that the monolithic 3D (M3D) static random access memory (SRAM) with gate and S/D bottom contact (GBC and SDBC) schemes (SRAMSDGBC) and analyzed they could significantly improve the power, performance, and area (PPA)
Externí odkaz:
https://doaj.org/article/bca9431751f1470ea8f23037fbb1d625
Autor:
Sanguk Lee, Jinsu Jeong, Bohyeon Kang, Seunghwan Lee, Junjong Lee, Jaewan Lim, Hyeonjun Hwang, Sungmin Ahn, Rockhyun Baek
Publikováno v:
Nanomaterials, Vol 13, Iss 5, p 868 (2023)
This study proposed a novel source/drain (S/D) extension scheme to increase the stress in nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using technology-computer-aided-design simulations. In three-dimensional integra
Externí odkaz:
https://doaj.org/article/61d55a28f66f47afb16870e9f1c43fd0
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 8, Pp 1272-1280 (2020)
In this article, by using neural network, we proposed a method to optimize Fully-Depleted (FD) Silicon-on-Insulator (SOI) Field-Effect-Transistor (FET) structures to maximize the on/off current ratio for 14-nm node (70-nm Gate Pitch) System-on-Chip (
Externí odkaz:
https://doaj.org/article/2aa003866b30422bb204d4dfb7416891
Publikováno v:
IEEE Access, Vol 8, Pp 35873-35881 (2020)
Excess source and drain (S/D) recess depth (TSD) variations were analyzed comprehensively as one of the most critical factors to DC/AC performances of sub 5-nm node Si-Nanosheet (NS) FETs for system-on-chip (SoC) applications. Variations of off-, on-
Externí odkaz:
https://doaj.org/article/dd3149784d574df689e44143c42e1a3f
Autor:
Sanguk Lee, Jinsu Jeong, Jun-Sik Yoon, Seunghwan Lee, Junjong Lee, Jaewan Lim, Rock-Hyun Baek
Publikováno v:
Nanomaterials, Vol 12, Iss 19, p 3349 (2022)
The inner spacer thickness (TIS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si
Externí odkaz:
https://doaj.org/article/eae37ed1f5aa4f5a8b48820cafb824ed
Publikováno v:
IEEE Access, Vol 7, Pp 75762-75767 (2019)
Structural advancements of 5-nm node bulk fin-shaped field-effect transistors (FinFETs) without punch-through-stopper (PTS) were introduced using fully calibrated TCAD for the first time. It is challenging to scale down conventional bulk FinFETs into
Externí odkaz:
https://doaj.org/article/ce4e468d4a354ae3b0c22507ccc13b45