Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Jinn-Shan Wang"'
A 439K gates/10.9KB SRAM/2–328 mW dual mode video decoder supporting temporal/spatial scalable video
Autor:
Jinn-Shan Wang, Cheng-An Chien, Yao-Chang Yang, Ching-Hwa Cheng, Hsiang-Hui Huang, Jiun-In Guo, Jia-Wei Chen, Hsiu-Cheng Chang, Chin-Hsien Wang
Publikováno v:
2009 IEEE Asian Solid-State Circuits Conference.
The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87fabc3bd3f6f68c26efa5e44c6f278f
https://doi.org/10.1109/asscc.2009.5357147
https://doi.org/10.1109/asscc.2009.5357147
Autor:
Wei-Sen Yang, Chun-Hao Chang, Ze-Min Chen, Yao-Chang Yang, Jinn-Shan Wang, Hsiu-Cheng Chang, Jiun-In Quo, Yao Li, Ching-Lung Su, Ching-Wen Chen, Jia-Wei Chen, Chien-Chang Lin
Publikováno v:
ISSCC
A dynamic quality-scalable H.264 video encoder is presented for power-adaptive video encoding. In 0.13mum CMOS technology, it requires 470kgates/13.3kB SRAM and consumes 7mW/183mW in encoding 30fps CIF/HD720 video. Compared to the state-of-the-art de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1fe54357da00608b80a2466549fc3de1
https://doi.org/10.1109/isscc.2007.373403
https://doi.org/10.1109/isscc.2007.373403
Autor:
Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jiun-In Guo, Jia-Wei Chen, Jinn-Shan Wang, Chin-Hsien Wang, Hsiang-Hui Huang, Ching-Hwa Cheng
Publikováno v:
2009 IEEE Asian Solid-State Circuits Conference; 2009, p197-200, 4p
Autor:
Hsiu-Cheng Chang, Jia-Wei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li, Chun-Hao Chang, Ze-Min Chen, Wei-Sen Yang, Chien-Chang Lin, Ching-Wen Chen, Jinn-Shan Wang, Jiun-In Quo
Publikováno v:
2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers; 2007, p280-603, 324p