Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Jin-Yub Lee"'
Autor:
Youngmin Jo, Ji-Yeon Shin, Dae Seok Byeon, Dong-Su Jang, Jin-Yub Lee, Dongku Kang, Anil Kavala, Tae-Sung Lee, Junha Lee, Seon-Kyoo Lee, Jai Hyuk Song, Byung-Hoon Jeong, Byung-Kwan Chun, Eunjin Song, Hwasuk Cho, Manjae Yang, Seung-jae Lee, Lee Jangwoo, Tongsung Kim, Jungdon Ihm, Daehoon Na, Chi-Weon Yoon
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:1129-1140
This article presents a 1.2-V, 1.8-Gb/s/pin 16-Tb NAND flash memory multi-chip package incorporating 16 dies of 1-Tb NAND flash memory and the third-generation F-chip. The proposed third-generation F-chip is developed to meet the performance requirem
Autor:
Moosung Kim, Sung Won Yun, Jungjune Park, Hyun Kook Park, Jungyu Lee, Yeong Seon Kim, Daehoon Na, Sara Choi, Youngsun Song, Jonghoon Lee, Hyunjun Yoon, Kangbin Lee, Byunghoon Jeong, Sanglok Kim, Junhong Park, Cheon An Lee, Jaeyun Lee, Jisang Lee, Jin Young Chun, Joonsuc Jang, Younghwi Yang, Seung Hyun Moon, Myunghoon Choi, Wontae Kim, Jungsoo Kim, Seokmin Yoon, Pansuk Kwak, Myunghun Lee, Raehyun Song, Sunghoon Kim, Chiweon Yoon, Dongku Kang, Jin-Yub Lee, Jaihyuk Song
Publikováno v:
2022 IEEE International Solid- State Circuits Conference (ISSCC).
Autor:
Jeon Hongsoo, In-Mo Kim, Jae-Ick Son, Chae-Hoon Kim, Seung-jae Lee, Byung-Hoon Jeong, Kyoung-Tae Kang, Lee Ho-Jun, Kwon Taehong, Pansuk Kwak, Jae-Yun Lee, Jai-Hyuk Song, D. Chris Kang, Jeong-yun Yun, Jin-Yub Lee, Cheon An Lee, Yo-Han Lee, Sang-Won Shim, Ho-joon Kim, Sung-Hoon Kim, Sanggi Hong, Sang-Won Park, Choi Yonghyuk, Myeong-Woo Lee, Jonghoon Park, Jongchul Park, Bong-Kil Jung, Han-sol Kim, Ki-Sung Kim, Jun-young Ko, Eung-Suk Lee, Sang-Wan Nam, Hogil Lee, Won-Tae Kim, Kyung-Min Kang, Chi-Weon Yoon, Ji-Ho Cho, Junha Lee, Yoon-Sung Shin, Dae Seok Byeon, Jung-ho Song, Seung-Hyun Moon, Jaedoeg Lyu, Jongyeol Park
Publikováno v:
ISSCC
The exponential data size growth in high-speed networks is a key motivator for nonvolatile memory development. To support this demand, higher density NAND is required: with a smaller cell size and higher interface speed. Generally, scaling down NAND
Publikováno v:
ICEIC
In this paper, design challenges and key technologies to overcome the hurdles for the future 3D NAND are introduced. More specifically, state-of-the-art solutions for higher density, lower cost and higher bandwidth NAND is covered in detail.
Publikováno v:
ITC
Post fabrication process is becoming more and more important as memory technology becomes complex, in the bid to satisfy target performance and yield across diverse business domains, such as servers, PCs, automotive, mobiles, and embedded devices, et
Autor:
HyunWook Park, Doohyun Kim, Jae Doeg Yu, Hyun-Jun Yoon, Jonghoon Park, Kye-Hyun Kyung, Hyung-Gon Kim, Jinbae Bang, Chulbum Kim, Jeong-Don Ihm, Yong-Ha Park, Seung-Bum Kim, Woopyo Jeong, Hwajun Jang, Ji-Young Lee, Il Han Park, Nahyun Kim, Pansuk Kwak, Yang-Lo Ahn, Ki-Tae Park, Jong-Hoon Lee, Sanggi Hong, Hyun-Jin Kim, Park Jiyoon, Dae Seok Byeon, Jin-Yub Lee, Young-don Choi, Moosung Kim, Nayoung Choi, Seung-Hwan Song
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:124-133
A 64-word-line-stacked 512-Gb 3-b/cell 3-D NAND flash memory is presented. After briefly examining the challenges that occur to a stack, several technologies are suggested to resolve the issues. For performance enhancement, a novel program method hid
Autor:
Yunhee Choi, Jindo Byun, Bong-Kil Jung, Hyeonggon Kim, Dae-Seok Byeon, Sung-Hoon Kim, Ki-Sung Kim, Yena Lee, Chang-Bum Kim, Chan-Jin Park, Han-Sung Joo, Jaehwan Kim, Young-don Choi, Hyun-Jin Kim, Seungwoo Yu, Nahyun Kim, Jin-Yub Lee, Youngmin Jo, Anil Kavala, Lee Jangwoo, Kye-Hyun Kyung, Jeong-Don Ihm, Kwang-won Kim, Daehoon Na, Pansuk Kwak, Park Jung-June, Kitae Park
Publikováno v:
2017 Symposium on VLSI Circuits.
A 1.2 V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package incorporating 16-die stacked 512-Gb NAND flash memories and F-Chip is presented. To meet the performance requirements of storage devices for higher capacity and faster data throughput, the
Autor:
Dae-Woon Kang, Chunan Lee, Jin-Yub Lee, Hyung-Gon Kim, Kitae Park, HyunWook Park, Moosung Kim, Sangki Hong, Sung-Hoon Lee, Kye-Hyun Kyung, Jeong-Don Ihm, In-Mo Kim, Inryul Lee, Ji-Young Lee, Ji-Sang Lee, Hyun-Jun Yoon, Seung-Hwan Song, Dongkyu Yoon, Young-don Choi, Yelim Kwon, Yong-Ha Park, Sung-Hoon Kim, Ji-Ho Cho, Jaedoeg Yu, Park Jiyoon, Doohyun Kim, Nayoung Choi, Nahyun Kim, Chulbum Kim, Pansuk Kwak, Hyun-Jin Kim, Jong-Hoon Lee, Woopyo Jeong, Hwajun Jang, Jonghoon Park, Byung-Hoon Jeong, Won-Tae Kim, Young-Sun Min, Yang-Lo Ahn, Ki-Sung Kim, Seung-Bum Kim, Dae-Seok Byeon, Jinbae Bang, Park Il-Han
Publikováno v:
ISSCC
The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra
Autor:
Dae-Seok Byeon, Kyung-Hwa Kang, Yongsu Choi, Jeon Hongsoo, Hyung-Gon Kim, Minseok Kim, Jeong-Don Ihm, Seon-Kyoo Lee, Kye-Hyun Kyung, Sungwhan Seo, Sung-Min Joe, Jin-Yub Lee, Su-Chang Jeon, Kitae Park, Byung-Hoon Jeong, HyunWook Park, Moosung Kim, Kim Su-Yong, Sung-Won Yun, Sangbum Yun, Young-Min Kim, Park Jiyoon, Hyang-ja Yang, Jong-Hoon Lee, Yong-Sik Yim, Sungkyu Jo, Byung-Kyu Cho, Hyejin Yim, Makoto Hirano, Jonghoon Park, Tae-eun Kim, Deok-kyun Woo, Lee Kang-Bin, Chan-Ho Kim, Hoosung Kim, Jongyeol Park, Jung-no Im, Yang-Lo Ahn, Seung-jae Lee, Jeong-Hyuk Choi, Park Il-Han, Minsu Kim, Jin-Tae Kim, Dooho Cho, Ho-Kil Lee
Publikováno v:
ISSCC
NAND flash memory is widely used as a cost-effective storage with high performance [1–2]. This paper presents a 128Gb multi-level cell (MLC) NAND flash memory with a 150 cells/string structure in 14nm CMOS that can be used as a cost-effective stora
Autor:
Jin-Yub Lee, Yong Hoon Kang, Dae-Yong Kim, Sang-Hoon Lee, Jong Yeol Park, Pyungmoon Jang, Yun Ho Choi, Minseok Kim, Jong Nam Baek, Jun-Yong Park, Chan-Ho Kim, Joon Young Kwak, Sang Won Hwang, You-Sang Lee, Su Chang Jeon, Yong-Taek Jeong, Jin-Kook Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:507-517
High-voltage analog circuits, including a novel high-voltage regulation scheme, are presented with emphasis on low supply voltage, low power consumption, low area overhead, and low noise, which are key design metrics for implementing NAND Flash memor