Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Jin-Seung Son"'
Publikováno v:
Transactions of the Korean Society of Mechanical Engineers A. 26:764-774
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b310d3cf065558d5ef819f0a5798c8b9
https://doi.org/10.3795/ksme-a.2002.26.4.764
https://doi.org/10.3795/ksme-a.2002.26.4.764
Publikováno v:
IEEE Transactions on Consumer Electronics. 38:208-213
The causes of skipping by sound pressure of a speaker in a compact disk player were studied through the analysis of the error signal from the optical pickup and the modal analysis. It was ascertained that skipping was induced by the nodal circle mode
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a3af4a0882b9a85ec0da37a81675ce0b
https://doi.org/10.1109/30.156685
https://doi.org/10.1109/30.156685
Publikováno v:
IEEE 1992 International Conference on Consumer Electronics Digest of Technical Papers.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1c148ea7335433a107cbdf28c81c618b
https://doi.org/10.1109/icce.1992.697143
https://doi.org/10.1109/icce.1992.697143
Autor:
Hoi-Jun Yoo, Seung-Jun Lee, Kee-Woo Park, Chang-Ho Chung, Kye-Hwan Oh, Sang-Ho Shin, Ki-Hong Park, Jeong-Dong Han, Seok-Tae Kim, Jin-Seung Son, Wi-Sik Min
Publikováno v:
Digest of Technical Papers., Symposium on VLSI Circuits..
A 32 bit-wide 256 M synchronous DRAM (SDRAM) has been developed. The major design effort has been focused on minimizing the operating current at high clock frequencies to suppress power-line bouncing. The key techniques are split-bank architecture, m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::70917371b3c17f00cba84ce9fed85536
https://doi.org/10.1109/vlsic.1995.520711
https://doi.org/10.1109/vlsic.1995.520711
Autor:
Hoi-Jun Yoo, Chang-Ho Chung, Hak-Jun Oh, Ki-Hong Park, Jin-Seung Son, Wi-Sik Min, Kee-Woo Park, Kye-Hwan Oh, Seung-Jun Lee, Jeong-Dong Han, Ki-Won Kwon
Publikováno v:
Proceedings ISSCC '95 - International Solid-State Circuits Conference.
A 256 Mb synchronous DRAM with 8 banks of 32 Mb arrays introduces (1) post charge logic in the critical timing paths, (2) a wave pipelining in the data path and (3) hierarchical I/O architecture. This simplifies the latency control and leads to a ful
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b78a3714beb807c4b66deda24fb75a1b
https://doi.org/10.1109/isscc.1995.535543
https://doi.org/10.1109/isscc.1995.535543
Publikováno v:
IEEE Transactions on Consumer Electronics; 1992, Vol. 38 Issue 3, p208-213, 6p
Autor:
Hoi-Jun Yoo, Kee-Woo Park, Chang-Ho Chung, Seung-Jun Lee, Hak-Jun Oh, Jin-Seung Son, Ki-Hong Park, Ki-Won Kwon, Jeong-Dong Han, Wi-Sik Min, Kye-Hwan Oh
Publikováno v:
Proceedings ISSCC '95 - International Solid-State Circuits Conference; 1995, p250-251, 2p
Autor:
Seung-Jun Lee, Kee-Woo Park, Chang-Ho Chung, Jin-Seung Son, Ki-Hong Park, Sang-Ho Shin, Seok-Tae Kim, Jeong-Dong Han, Hoi-Jun Yoo, Wi-Sik Min, Kye-Hwan Oh
Publikováno v:
Digest of Technical Papers, Symposium on VLSI Circuits; 1995, p113-114, 2p
Publikováno v:
IEEE 1992 International Conference on Consumer Electronics Digest of Technical Papers; 1992, p90-91, 2p
Conference
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