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Autor:
Sung-Jin Whang, Byoungho Lee, Joo-Hee Han, Young Jin Lee, Jin-Hae Choi, Jinwoong Kim, MinSoo Kim, Seung-Ho Pyi, Dong-Sun Sheen
Publikováno v:
2011 IEEE International Interconnect Technology Conference.
This paper presents an optimized Co silicide process to realize low resistance multilayered word lines in 3D NAND Flash device. With CVD Co method, it is obtained that the step coverage is about 97% at the aspect ratio of 15∶1 trench. Co silicide i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::952a7d2626f238e3182079f2d4b5b18c
https://doi.org/10.1109/iitc.2011.5940281
https://doi.org/10.1109/iitc.2011.5940281
