Zobrazeno 1 - 10
of 57
pro vyhledávání: '"Jiin Chuan Wu"'
Publikováno v:
IEEE Transactions on Power Electronics. 22:1836-1846
A monolithic current-mode pulse width modulation (PWM) step-down dc-dc converter with 96.7% peak efficiency and advanced control and protection circuits is presented in this paper. The high efficiency is achieved by "dynamic partial shutdown strategy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3db2a8aa79a3c38d413ae3e7e4967572
https://doi.org/10.1109/tpel.2007.904237
https://doi.org/10.1109/tpel.2007.904237
Autor:
Jiin-Chuan Wu, Hao-Ping Hong
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:152-155
When MOSFET is used as a power switch, it is essential to prevent reverse current flow through the parasitic body diodes under reverse voltage condition. A new built-in reverse voltage protection circuit for MOSFETs has been developed. In this design
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::989c9cbff706029733c6fadef8d5fa22
https://doi.org/10.1109/4.896242
https://doi.org/10.1109/4.896242
Publikováno v:
Solid-State Electronics. 43:375-393
A novel dynamic-floating-gate technique is proposed to improve ESD robustness of the CMOS output buffers with small driving/sinking currents. This dynamic-floating-gate design can effectively solve the ESD protection issue which is due to the differe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::42123b5442576070e6d54057f1be3823
https://doi.org/10.1016/s0038-1101(98)00262-7
https://doi.org/10.1016/s0038-1101(98)00262-7
Autor:
Jiin-Chuan Wu, Pang-Cheng Yu
Publikováno v:
IEEE Journal of Solid-State Circuits. 34:116-119
Due to the large number of output buffers on a column driver chip of a flat-panel display, the quiescent current and die area of the output buffer must be minimized. This paper presents a low static power, large output swing, and wide operating volta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c3d216a22697fbb2991f9ff9ff148ce
https://doi.org/10.1109/4.736665
https://doi.org/10.1109/4.736665
Autor:
Jiin-Chuan Wu, Chi-Chang Wang
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:598-603
A separately self-biased transistor-transistor logic (TTL)-to-CMOS input buffer (SSIB) is proposed. Its logic threshold voltage is kept at 1.4 V when supply voltage is changed from 3.3 V to 5 V, making it suitable for 3.3-V/5-V dual voltage applicati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f0d1f1d16f62ec7d4ee0d7d0ce62f766
https://doi.org/10.1109/4.663565
https://doi.org/10.1109/4.663565
Autor:
Hun-Hsien Chang, Jiin-Chuan Wu
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1572-1575
A high-speed complementary metal-oxide-semiconductor (CMOS) programmable divide-by-N frequency divider was proposed. Using a new end-of-count (EOC) detecting and reloading algorithm, the reloading delay is distributed over three clock cycles, which i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e363e7f6b7b68836f53c88fc40cdc3ad
https://doi.org/10.1109/4.720407
https://doi.org/10.1109/4.720407
Autor:
Jiin-Chuan Wu, Chi-Chang Wang
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:852-860
Conventional charge pump circuits use a fixed switching frequency that leads to power efficiency degradation for loading less than the rated loading. This paper proposes a level shifter design that also functions as a frequency converter to automatic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::297a24c0f98cc97868bbd6c92a3443a4
https://doi.org/10.1109/4.585287
https://doi.org/10.1109/4.585287
Autor:
Chung-Hsien Tso, Jiin-Chuan Wu
Publikováno v:
IEEE Power Electronics Letters. 1:61-63
This paper presents a ripple control buck regulator for stepping down high-voltage adaptor or battery supplies to low-voltage CPU core supply in notebook computers. Methods and circuits are proposed to achieve fixed switching frequency operation. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4efaccb7a58089266b68c23fd80d448f
https://doi.org/10.1109/lpel.2003.819643
https://doi.org/10.1109/lpel.2003.819643
Autor:
Tzu-Chao Lin, Jiin-Chuan Wu
Publikováno v:
Proceedings. IEEE Asia-Pacific Conference on ASIC.
This paper describes a 3 V 8-bit 50 MSPS two-step analog-to-digital converter implemented in a 0.35 /spl mu/m 1P4M logic CMOS process. A PMOS biased in accumulation mode was used as a coupling capacitor in this ADC, so that the more expensive mixed m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fbd1230c8a6d598bbecfb159ac67d3b3
https://doi.org/10.1109/apasic.2002.1031561
https://doi.org/10.1109/apasic.2002.1031561
Autor:
Ming-Chan Weng, Jiin-Chuan Wu
Publikováno v:
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360).
A fully integrated CMOS temperature sensor is presented. The design uses parasitic substrate bipolar transistors as a temperature sensor. The temperature and reference signals are first converted into current signals by a voltage-to-current converter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9eac98f621243b2e74ad004f30b2b060
https://doi.org/10.1109/apasic.1999.824042
https://doi.org/10.1109/apasic.1999.824042