Zobrazeno 1 - 10
of 26
pro vyhledávání: '"Jih-Sheng Shen"'
Autor:
Jih-Sheng Shen, 沈日昇
101
Due to advanced process technologies, crosstalk interferences and high dynamic power consumption in a Network-on-Chip (NoC) are two increasingly problematic design issues. These problems become more severe in a NoC because of the large numbe
Due to advanced process technologies, crosstalk interferences and high dynamic power consumption in a Network-on-Chip (NoC) are two increasingly problematic design issues. These problems become more severe in a NoC because of the large numbe
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/21937933312113038317
Autor:
Jih-sheng Shen, 沈日昇
93
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functi
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functi
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/00423840281880272897
Autor:
Jih-Sheng Shen, Pao-Ann Hsiung
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22:1777-1790
Crosstalk interferences and high dynamic power consumption in a network-on-chip (NoC) are two increasingly problematic design issues. Using data codecs can reduce the switching activities on wires that cause crosstalk interferences and high dynamic p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::caf0c3acaad5d460dd20d6e8f6875be7
https://doi.org/10.1109/tvlsi.2013.2278334
https://doi.org/10.1109/tvlsi.2013.2278334
Publikováno v:
Computers & Electrical Engineering. 39:453-464
To solve two increasingly problematic issues, namely crosstalk interferences and wire power consumption, in a Network-on-Chip (NoC), Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC) is proposed. It include
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5f94f95c28e44f1b9dfd8ae6b27d80b5
https://doi.org/10.1016/j.compeleceng.2012.09.013
https://doi.org/10.1016/j.compeleceng.2012.09.013
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems. 4:1-32
With the gradually fading distinction between hardware and software, it is now possible to relocate tasks from a microprocessor to reconfigurable logic and vice versa. However, existing hardware-software scheduling can rarely cope with such runtime t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::213214dafb1edfe4ca4e8226d74f11b2
https://doi.org/10.1145/1857927.1857936
https://doi.org/10.1145/1857927.1857936
Publikováno v:
Journal of Systems Architecture. 56:545-560
To facilitate the development of the dynamically partially reconfigurable system (DPRS), we propose a model-based platform-specific co-design (MPC) methodology for DPRS with hardware virtualization and preemption. For DPRS analysis and validation, a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4996b7423f76e9c73e5acc4f3cd9c310
https://doi.org/10.1016/j.sysarc.2010.07.007
https://doi.org/10.1016/j.sysarc.2010.07.007
Publikováno v:
Journal of Systems Architecture. 56:88-102
The dynamic partial reconfiguration technology of FPGA has made it possible to adapt system functionalities at run-time to changing environment conditions. However, this new dimension of dynamic hardware reconfigurability has rendered existing CAD to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a9c3c3bd31136399150683696082d7e3
https://doi.org/10.1016/j.sysarc.2009.11.007
https://doi.org/10.1016/j.sysarc.2009.11.007
Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 13:1-31
As the number of cores on a chip increases, power consumed by the communication structures takes a significant portion of the overall power budget. In this article, we first propose a circuit-switched interconnection architecture which uses crossroad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::98a88c65a9c6dda8e46e2385d43c9322
https://doi.org/10.1145/1297666.1297678
https://doi.org/10.1145/1297666.1297678
Publikováno v:
HPCS
Due to the need to support concurrent executions of versatile applications, the system complexity, in terms of the number of cores, is drastically increased from tens to hundreds or thousands of cores. These complex systems usually contain heterogene
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4b99a474d72b0d6e0b1a8d12232618d
https://doi.org/10.1109/hpcsim.2014.6903730
https://doi.org/10.1109/hpcsim.2014.6903730
Autor:
Pao-Ann Hsiung, Chun-Yang Peng, Hung-Lin Chao, Cheng-Chien Wu, Ken-Shin Huang, Jih-Sheng Shen, Chun-Hsien Lu
Publikováno v:
FPT
The Fast Fourier Transform (FFT) has been one of the most popular and widely-used transform functions in communication hardware designs. With growing digital convergence, a single device needs to support multiple communication protocols, all of which
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc2b3b833632c559d068048af925a5e2
https://doi.org/10.1109/fpt.2013.6718405
https://doi.org/10.1109/fpt.2013.6718405