Zobrazeno 1 - 10
of 110
pro vyhledávání: '"Jieh-Tsorng Wu"'
Autor:
Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu, Shiuh-hua Wood Chiang, Chien-Nan Jimmy Liu, Hung-Ming Chen
Publikováno v:
Proceedings of the 28th Asia and South Pacific Design Automation Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c6847c9f950f9a22fe684aec3a9ad237
https://doi.org/10.1145/3566097.3567878
https://doi.org/10.1145/3566097.3567878
Autor:
Alexander Petrie, Mau-Chung Frank Chang, Yong Qu, Hunter Jensen, Eric Swindlehurst, Jieh-Tsorng Wu, Yixin Song, Yen-Cheng Kuan, Shiuh-hua Wood Chiang
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:2347-2359
An 8-bit 10-GHz 8 $\times $ time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporates an aggressively scaled digital-to-analog converter (DAC) with grouped capacitors in a symmetrical structure to afford
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6061bafb88d0c8213e6c63685456d7fa
https://doi.org/10.1109/jssc.2021.3057372
https://doi.org/10.1109/jssc.2021.3057372
Autor:
Sheng-Hui Liao, Jieh-Tsorng Wu
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:2523-2531
A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::04969125ec60eddbd2b4c30ba9386f56
https://doi.org/10.1109/jssc.2019.2925273
https://doi.org/10.1109/jssc.2019.2925273
Autor:
Chih-Min Chang, Jieh-Tsorng Wu
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 64:1106-1117
A digital class-D amplifier (CDA) converts an audio digital stream into sound directly and power-efficiently. It first encodes the pulse-code-modulated audio input into a digital pulse-width-modulated (PWM) signal. It needs a digital-to-pulse convert
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1bc0f75bf699db37673eff3cde4a01a5
https://doi.org/10.1109/tcsi.2016.2634016
https://doi.org/10.1109/tcsi.2016.2634016
Autor:
Alexander Petrie, Eric Swindlehurst, Yen-Cheng Kuan, Hunter Jensen, Mau-Chung Frank Chang, Jieh-Tsorng Wu, Yixin Song, Shiuh-hua Wood Chiang
Publikováno v:
ESSCIRC
An 8-bit 10-GHz $8\times $ time-interleaved SAR ADC in 28-nm CMOS incorporates an aggressively scaled DAC with grouped capacitors in a symmetrical comb structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A dual-path b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::8de752802983c3bbe1b8be297cadf2f5
https://doi.org/10.1109/esscirc.2019.8902621
https://doi.org/10.1109/esscirc.2019.8902621
Autor:
Sheng-Hui Liao, Jieh-Tsorng Wu
Publikováno v:
CICC
A 2-1 MASH switched-capacitor delta-sigma modulator was fabricated using a 65 nm CMOS technology. We constantly alternate the circuit configurations of its internal integrators to optimize power consumption. The integrators are accelerated only when
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f100f614a4a46e56633096ed82a102ab
https://doi.org/10.1109/cicc.2018.8357086
https://doi.org/10.1109/cicc.2018.8357086
Autor:
Yung-Hui Chung, Jieh-Tsorng Wu
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:557-566
This paper presents a digital-subranging (sub-R) analog-to-digital conversion (ADC) architecture to improve the operation speed of sub-R ADCs. Long latency between coarse and fine conversions will slow down the conventional sub-R ADCs. The proposed d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7cef57f50a449ca76a2c3ace3da9dafc
https://doi.org/10.1109/tvlsi.2014.2312211
https://doi.org/10.1109/tvlsi.2014.2312211
Autor:
Su-Hao Wu, Jieh-Tsorng Wu
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:2170-2179
A fourth-order discrete-time delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. It combines low-complexity circuits and digital calibrations to achieve high speed and high performance. The DSM is a cascade of two second-order l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::042c3e4560ed3c19de415e53d3b7af31
https://doi.org/10.1109/jssc.2013.2264137
https://doi.org/10.1109/jssc.2013.2264137
Autor:
Jieh-Tsorng Wu, Bing-Nan Fang
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:670-683
A 10-bit pipelined ADC was fabricated using a 65 nm CMOS technology. To reduce power consumption, switching opamps are used. These switching opamps are designed to have a short turn-on time. Digital background calibration is employed to correct the A
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::467a5025de905d851fa3cbccbc8f651c
https://doi.org/10.1109/jssc.2012.2233332
https://doi.org/10.1109/jssc.2012.2233332
Autor:
Jieh-Tsorng Wu, Yun Chai
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:2905-2915
A 10-bit 200-MS/s pipelined ADC was fabricated using a standard 65 nm CMOS technology. We propose a dual-path amplification technique for residue generation. We split the pipeline stage into a coarse-stage multiplying digital-to-analog converter (MDA
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::83c61b484e255b7bbd1331105dd5de54
https://doi.org/10.1109/jssc.2012.2217872
https://doi.org/10.1109/jssc.2012.2217872