Zobrazeno 1 - 10
of 23
pro vyhledávání: '"JiHeon Yu"'
Publikováno v:
2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS).
In mobile platforms, RFI problems caused by the noises on switched-mode power supplies (SMPSs) have arisen. The SMPS noise which affects RF bands is generated by the voltage ringing at the switch transitions in the SMPS operation. This voltage ringin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::82b05f6ed0142277f14fdf8926728a14
https://doi.org/10.1109/edaps.2016.7893115
https://doi.org/10.1109/edaps.2016.7893115
Publikováno v:
2015 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS).
In this paper, a high speed channel insertion loss estimation method for meshed ground is proposed. A 2.5D EM (Electromagnetic) tool spends less time to do simulation. But, it cannot analyze meshed ground structure. By converting meshed ground into s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce44a266094d4d53dfe0b30f73ce82c7
https://doi.org/10.1109/edaps.2015.7383684
https://doi.org/10.1109/edaps.2015.7383684
Publikováno v:
IEEE Design & Test of Computers. 23:212-219
System-in-package provides highly integrated packaging with high-speed performance. Many SiP packages contain low-cost 3D stacked chips interconnected by fine wire bonds. In a high-frequency spectrum, these wire bonds can cause discontinuities causin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe0b52ee3298250cc30aa970b3b71741
https://doi.org/10.1109/mdt.2006.78
https://doi.org/10.1109/mdt.2006.78
Autor:
Joungho Kim, Hoi-Jun Yoo, Hyungsoo Kim, Daehyun Chung, Choonheung Lee, Kicheol Bae, Jiheon Yu, Jinhan Kim, Chunghyun Ryu
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:274-286
This paper presents a chip-package hybrid clock distribution network and delay-locked loop (DLL) with which to achieve extremely low jitter clock delivery. The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5cbed93c0c3b76b851e880ca7eb0c44f
https://doi.org/10.1109/jssc.2005.859882
https://doi.org/10.1109/jssc.2005.859882
Autor:
SeungJae Lee, Daehyun Chung, Jiheon Yu, Kicheol Bae, Joungho Kim, Jinhan Kim, Chunghyun Ryu, Choonheung Lee
Publikováno v:
IEEE Microwave and Wireless Components Letters. 16:651-653
Cascaded repeaters are indispensable circuit elements in conventional on-chip clock distribution networks due to heavy loss characteristics of on-chip global interconnections. However, cascaded repeaters cause significant jitter and skew problems in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::97986a6876763bad5eb40d83cc309faf
https://doi.org/10.1109/lmwc.2006.885604
https://doi.org/10.1109/lmwc.2006.885604
Autor:
GaWon Kim, Choonheung Lee, SeungJae Lee, Jiheon Yu, Jin Young Kim, GyuIck Jung, HeeYeoul Yoo, Nozard Karim
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
In this paper, coreless flip-chip BGA in Amkor Technology will be introduced with two options. First option is a revised coreless substrate design with layer reduction from original core substrate design of flip-chip BGA package and the second one is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::53799a4c4ddb85b5855b7636bc0b7a85
https://doi.org/10.1109/ectc.2011.5898573
https://doi.org/10.1109/ectc.2011.5898573
Publikováno v:
2011 IEEE 15th Workshop on Signal Propagation on Interconnects (SPI).
Semiconductor markets require continuous device miniaturization while the I/O density and the frequency/speed of operation increase. Maintaining acceptable signal integrity at the system level has become more challenging than ever. Impedance control
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::160f00deedfc3e7318c56eaa1a643b73
https://doi.org/10.1109/spi.2011.5898843
https://doi.org/10.1109/spi.2011.5898843
Autor:
GaWon Kim, Choonheung Lee, Jiheon Yu, Kicheol Bae, Jin Young Kim, SangWon Kim, HeeYeoul Yoo, SeungJae Lee
Publikováno v:
3rd Electronics System Integration Technology Conference ESTC.
In this paper, developments of wafer level fan-out (WLFO) technology using organic substrates, ajinomoto build-up film (ABF) with laser ablation process and buried pattern PCB, are introduced for low cost and high electrical performance not only on l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fa0bfbdcee9e3b007d53ba7bcc937e90
https://doi.org/10.1109/estc.2010.5642956
https://doi.org/10.1109/estc.2010.5642956
Autor:
GaWon Kim, Ozgur Misman, TaeKi Kim, Jin Young Kim, Jiheon Yu, SeungJae Lee, Kicheol Bae, Sangwoong Lee
Publikováno v:
2010 IEEE CPMT Symposium Japan.
In this paper, package co-design procedure with electrical simulation supported by Amkor Technology will be described and design trade-off for effective power/ground plane design in SBGA package will be discussed. Two models of SBGA design, which has
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dae1d3f658a340a250358bd1cb661677
https://doi.org/10.1109/cpmtsympj.2010.5679670
https://doi.org/10.1109/cpmtsympj.2010.5679670
Autor:
SeungJae Lee, BooYang Jung, Kicheol Bae, Choonheung Lee, Jiheon Yu, YoungSuk Chung, SangWon Kim, Brett Arnold Dunlap, Nozad Karim, Jin Young Kim, ChanHa Hwang
Publikováno v:
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).
In this paper, development of wafer level fan-out (WLFO) technology using ajinomoto build-up film (ABF) substrate with laser ablation process is introduced for low cost and high electrical performance for millimeter wave application. Wafer level fan-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::90bfe023c7c07ef8920e8f75b61c5bf4
https://doi.org/10.1109/ectc.2010.5490804
https://doi.org/10.1109/ectc.2010.5490804