Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Ji Hwan (Paul) Chun"'
Publikováno v:
European Test Symposium
This paper presents a new method for random jitter measurement on systems-on-a-chip (SoCs) by exploiting shmoo plotting in automatic test equipment (ATE). After finding the maximum operating frequency of a microprocessor using functional test pattern
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a1d0e7c4ed4c77a7e45641526a39083d
https://doi.org/10.1109/ets.2012.6233022
https://doi.org/10.1109/ets.2012.6233022
Publikováno v:
VTS
Conventional test for high speed serial links requires expensive test equipment to meet the standard < 10−12 bit error rate (BER) requirement. Although timing margining loop-back tests are cost effective, phase interpolator (PI) circuitry needs to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f13bfc53975e7548545252af26cda230
https://doi.org/10.1109/vts.2012.6231092
https://doi.org/10.1109/vts.2012.6231092
Publikováno v:
Asian Test Symposium
This paper describes a RMS value measurement technique for random jitter. A jittery clock signal is combined with a reference clock signal using an OR operation and an AND operation in sequence, and the pulse width outputs modulated by the amount of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f7964491001974819a67ec691914b86
https://doi.org/10.1109/ats.2009.38
https://doi.org/10.1109/ats.2009.38
Publikováno v:
European Test Symposium
Accurate generation of circuit specifications from test signatures is a difficult problem, since analytical expressions cannot precisely describe the nonlinear relationships between signatures and specification. In addition, it is difficult to precis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8284b9668996ad52e7200dcfcfe6f13f
https://doi.org/10.1109/ets.2006.37
https://doi.org/10.1109/ets.2006.37
Publikováno v:
ITC
Signatures used in low-cost schemes for testing analog and mixed-signal circuits do not directly represent or characterize the behavior of the device-under-test (DUT), since the lossy compression or complicated mathematical relations used can result
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9659006a846ae5396ec53a2cabac934e
https://doi.org/10.1109/test.2004.1387414
https://doi.org/10.1109/test.2004.1387414
Publikováno v:
ACM Great Lakes Symposium on VLSI
Our method extracts the linearity of on-chip high speed data converters with minimum area overhead. With a loop-back setup in the presence of noise, differential nonlinearities (DNLs) and integral nonlinearities (INLs) of analog-to-digital converters
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c4733900c058241fc3596b099a4ec688
https://doi.org/10.1145/988952.989031
https://doi.org/10.1145/988952.989031