Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Jhy-Rong Chen"'
Autor:
Jhy-Rong Chen, 陳志榮
83
In this thesis, a novel and efficient synthesis method for high order lowpass and bandpass Sigma-Delta modulators is proposed for the determination of system design parameters according to system specifications and rigorous stability constrai
In this thesis, a novel and efficient synthesis method for high order lowpass and bandpass Sigma-Delta modulators is proposed for the determination of system design parameters according to system specifications and rigorous stability constrai
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/60142410502792507790
Publikováno v:
ISSCC
The demand for modern portable smart devices is growing at an unprecedented rate, which speeds up the development of the next-generation wireless-LAN (WLAN) standard. To improve spectrum efficiency and serve more users in crowded areas while increasi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d72dc0b65fbfe5f373da1f369ee81beb
https://doi.org/10.1109/isscc.2019.8662416
https://doi.org/10.1109/isscc.2019.8662416
Autor:
Song-Yu Yang, Shin-Fu Chen, Tzung-Han Wu, Sheng Jau Wong, Jhy-Rong Chen, George Chien, Hsi-Ming Yang, Chi-Hsueh Wang, Augusto Marques, Ta-Hsin Lin, Li-Shin Lai, Wei-Kai Hong, Chinq-Shiun Chiu, Caiyi Wang, Hung-Chieh Tsai, Hsiang-Hui Chang, Hsiao-Wei Chen, Chieh-Chuan Chin
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:1161-1173
A quad-band GSM/GPRS/EDGE cellular system, implemented in 65-nm CMOS, is integrated in a multimedia SoC with BT and FM. A low-IF receiver with digital IRR tracking is selected for its smaller area and better noise figure. The receiver achieves a sens
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::501ce291f46144aded1ca746d7a2096e
https://doi.org/10.1109/jssc.2013.2253716
https://doi.org/10.1109/jssc.2013.2253716
Autor:
Chris Beale, Li-Shin Lai, Fahd Ben Abdeljelil, Walid Youssef Ali-Ahmad, Tze Yee Sin, Wen-Chang Lee, Christophe Beghein, David Stephen Ivory, Jhy-Rong Chen, Ivan Siu-Chuang Lu, Charles Chiu, Jon Strange, Chi-Wei Fan, Ta-Hsin Lin, Chih-Hao Sun, Hsiang-Hui Chang, Shao-Hung Lin, Dimitris Nalbantis, Hao-Tang Shih, Paul Muller, Hsin-Hua Chen, Sheng-Jui Huang
Publikováno v:
2014 IEEE Radio Frequency Integrated Circuits Symposium.
A 40 nm CMOS transceiver supports 10 bands of HSPA+ and quad-band GSM/EDGE occupying 6.2 mm 2 of a Modem SoC. The TX supports up to 11 Mb/s HSUPA with minimal analog filtering and 42dB SNR for receive levels >-60 dBm.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d01136c03d9af9fcf6b47b0943089220
https://doi.org/10.1109/rfic.2014.6851678
https://doi.org/10.1109/rfic.2014.6851678
Publikováno v:
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 46:6-15
An automatic-design methodology for designing high-tolerance modulator coefficients for high-order sigma-delta modulators (SDMs) from system specifications is presented. The methodology covers many design concerns including SDM coefficient tolerances
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b7c3e605cbe59e769beeca5a99f1d8fb
https://doi.org/10.1109/82.749075
https://doi.org/10.1109/82.749075
Autor:
Weimin Shu, Osama Shana'a, Deyong Hu, Chin Heng Leow, Sheng Jau Wong, Ying Chow Tan, Jhy-Rong Chen, Xudong Jiang
Publikováno v:
2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).
A 76-108MHz FM Transmitter emits 120dBμVrms output signal using an embedded antenna on a PCB. A proposed on-chip calibration scheme digitally tunes an on-chip capacitor array to centre the embedded antenna resonance circuit with an external inductor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::512d2ad8a99d44c3cf563b279c8a4049
https://doi.org/10.1109/asscc.2013.6691017
https://doi.org/10.1109/asscc.2013.6691017
Autor:
Jhy-Rong Chen, Yuan Sun, Jing-Hong Conan Zhan, Hsuan-Yu Liu, Chih-Fan Liao, Min Chen, Chihun Lee, Kuo-Hao Chen, Chia-Jui Hsu, Wei-Kai Hong, Sheng-Jau Wong, Yu-Li Hsueh, Chunwei Chang, Hong-Kai Hsu, Osama Shana'a, Hong-Lin Chu, Chao-Hsin Lu, Eng Chuan Low, Deyong Hu, Guang-Kaai Dehng, George Chien, Kuan Chien-Wei, Yi-Hsien Cho, Weimin Shu, Chih-Hsien Shen, Yuan-Hung Chung, Jui-Lin Hsu, Tsung-Ming Chen, Li-Chun Ko, Jie-Wei Lai, Xudong Jiang
Publikováno v:
ISSCC
In recent years, the increasing popularity of mobile devices, such as smart-phones and tablets, is driving the demand for integrating multiple radios on a single SoC to reduce cost, form factor and external BOM [1]. These devices require ubiquitous w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::804e05f763d4d6a7c48defc4f98e2bef
https://doi.org/10.1109/isscc.2012.6176964
https://doi.org/10.1109/isscc.2012.6176964
Publikováno v:
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 39:753-756
Presents an efficient pipeline architecture to perform gray-scale morphologic operations. The features of the architecture are 1) lower hardware cost, 2) faster operation time in processing an image, 3) lower data access times from the image memory,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f457b9cbdf504a3d5892fb9189a472f
https://doi.org/10.1109/82.199903
https://doi.org/10.1109/82.199903
Publikováno v:
2008 IEEE Asian Solid-State Circuits Conference.
A 3-order multi-bit continuous-time delta-sigma ADC with clock timing calibration circuit is presented. The clock timing calibration circuit is proposed to ensure the stability of the continuous-time delta-sigma ADC and relax the bandwidth requiremen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::211ab753ecc6af7e27fcae2f668ce461
https://doi.org/10.1109/asscc.2008.4708804
https://doi.org/10.1109/asscc.2008.4708804
Autor:
Tai-Haur Kuo, Jhy-Rong Chen
Publikováno v:
1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
An exquisite high-order sigma delta (/spl Sigma//spl Delta/) modulator for specific application is hard to be achieved by a less experienced designer formerly. Now, a novel and efficient design method for high-order lowpass and bandpass /spl Sigma//s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84ff353abb88435535eb490b966ddf3c
https://doi.org/10.1109/iscas.1996.539795
https://doi.org/10.1109/iscas.1996.539795