Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Jhon-Jhy Liaw"'
Autor:
Hung-jen Liao, Fujiwara Hidehiro, Jhon-Jhy Liaw, Yen-Huei Chen, Po-Yi Huang, Cheng-Han Lin, Pan Hsien-Yu, Lin Chih-Yu, Jonathan Chang, Kao-Cheng Lin
Publikováno v:
ISSCC
Continued transistor scaling increases random $V_{t}$ variation, and wire routing resistance and capacitance; it degrades SRAM performance and results in SRAM design difficulties. Although dual-port (DP) SRAM is useful, because it can offer simultane
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a5b0c694376848a480e89f4704fc3af3
https://doi.org/10.1109/isscc.2019.8662415
https://doi.org/10.1109/isscc.2019.8662415
Autor:
Hank Cheng, M.C. Chiang, Hung-jen Liao, Fujiwara Hidehiro, Quincy Li, Kao-Cheng Lin, Jhon-Jhy Liaw, Lin Chih-Yung, Jonathan Chang, Yen-Huei Chen, Jih-Yu Lin, Wei Min Chan, Shien-Yang Wu, Singh Sahil Preet, Robin Lee, John Hung
Publikováno v:
ISSCC
FinFET technology has become a mainstream technology solution for post-20nm CMOS technology [1], since it has superior short-channel effects, better sub-threshold slope and reduced random dopant fluctuation. Therefore, it is expected to achieve bette
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c26de0f6c48079a20c338ffd78124311
https://doi.org/10.1109/jssc.2014.2349977
https://doi.org/10.1109/jssc.2014.2349977
Autor:
Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu
Publikováno v:
2017 IEEE International Solid-State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::767fe9e873b7144ea10dcc2b8bc11961
https://doi.org/10.1109/isscc.2017.7870333
https://doi.org/10.1109/isscc.2017.7870333
Autor:
S.Y. Chang, Hon-Jarn Lin, S.H. Yang, R. Chen, R.F. Tsui, Jhon-Jhy Liaw, S. M. Jang, M.C. Chiang, C. H. Hsieh, C.H. Yao, P N Chen, K T Lai, Y S Mor, Lin Chih-Yung, Chun-Kuang Chen, Kuang-Hsin Chen, Chia-Pin Lin, J.H. Chen, C.H. Tsai, Y. Ku, T. Miyashita, Ming-Huan Tsai, C. H. Lee, Chang Chih-Yang, Hou-Yu Chen, K.H. Pan, Shien-Yang Wu, Joy Cheng, C S Liang, Kuei-Shun Chen, C.H. Chang, Vincent S. Chang
Publikováno v:
2016 IEEE International Electron Devices Meeting (IEDM).
For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications is presented. This technology provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over our 16nm FinFET technology. A fully fun
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b45e5653ee5ec76f93d6159ac9161bd4
https://doi.org/10.1109/iedm.2016.7838333
https://doi.org/10.1109/iedm.2016.7838333
Autor:
C.Y. Lee, M.C. Chiang, Lin Chih-Yung, Kuei-Shun Chen, V.S. Chang, C.H. Yao, R. Chen, S.M. Jang, R.F. Tsui, C.H. Chang, Y.K. Wu, C.H. Tsai, T. Miyashita, Jhon-Jhy Liaw, Huicheng Chang, Shien-Yang Wu, Joy Cheng, K.H. Pan, Chang-Ta Yang, C. H. Hsieh, Kai-Yuan Ting, Y. Ku
Publikováno v:
2016 IEEE Symposium on VLSI Technology.
For the first time, we demonstrate the smallest, fully functional 32Mb 6-T high density SRAM reported in literature with scaled bulk FinFETs for CMOS technology beyond 10nm node. Scaled FinFET devices exhibit excellent electrostatic with DIBL of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8bc10b7b670a120907e7bb05eea60287
https://doi.org/10.1109/vlsit.2016.7573390
https://doi.org/10.1109/vlsit.2016.7573390
Autor:
Jhon-Jhy Liaw, Ching-Wei Wu, Yen-Huei Chen, Jonathan Chang, Wei Min Chan, Kao-Cheng Lin, Hung-jen Liao
Publikováno v:
VLSI Circuits
A total solution for 8T dual-port (DP) SRAM to improve its operating voltage range (V MIN /V MAX ) is proposed. Partial suppressed word-line (PSWL) technique improves the static noise margin (SNM) when both ports (A, B ports) access at the same time.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1ab970c6d1aff994de80e17fa4b98af
https://doi.org/10.1109/vlsic.2016.7573459
https://doi.org/10.1109/vlsic.2016.7573459
Autor:
Lin Chih-Yung, Hung-jen Liao, Fujiwara Hidehiro, Kao-Cheng Lin, Shin-Rung Wu, Dar Sun, M.C. Chiang, Li-Wen Wang, Jonathan Chang, Shien-Yang Wu, Jhon-Jhy Liaw, Yen-Huei Chen
Publikováno v:
ISSCC
FinFET technology has been adopted in the 16nm node because it provides superior l on /l off ratio, short-channel effect and local variation [1,2]. 2P-SRAM, which offers simultaneous read and write operations, is widely used for media processing beca
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8eda61c8cf11efbe749baf88d1d41ca2
https://doi.org/10.1109/isscc.2015.7063051
https://doi.org/10.1109/isscc.2015.7063051
Autor:
Lin Chih-Yung, Tze-Liang Lee, S.Y. Chang, R.F. Tsui, Ming-Huan Tsai, K.H. Pan, Joy Cheng, R. Chen, Kuei-Shun Chen, C.H. Yao, T. Yamamoto, M.C. Chiang, Y.K. Wu, T. Chang, Kai-Yuan Ting, J.H. Chen, Jhon-Jhy Liaw, S. M. Jang, C. H. Lee, S.H. Yang, Y. Ku, H. M. Lee, Vincent S. Chang, Hou-Yu Chen, Liang Min-Chang, H.T. Huang, S.Z. Chang, Yuan-Hung Chiu, Shien-Yang Wu, W. Chang, Chun-Kuang Chen, C.H. Tsai, T. Miyashita, C.H. Chang
Publikováno v:
2014 IEEE International Electron Devices Meeting.
Advancing the state-of-the-art 16nm technology reported last year, an enhanced 16nm CMOS technology featuring the second generation FinFET transistors and advanced Cu/low-k interconnect is presented. Core devices are re-optimized to provide additiona
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::11bb4678396bff26b458b0f2c0fbf969
https://doi.org/10.1109/iedm.2014.7046970
https://doi.org/10.1109/iedm.2014.7046970
Autor:
Chung-Cheng Wu, Carlos H. Diaz, Wei-Ming Chen, Yo-Sheng Lin, Rong-Ping Yang, Jhon-Jhy Liaw, Chih-Sheng Chang
Publikováno v:
IEEE Transactions on Electron Devices. 49:1034-1041
In this paper, we demonstrate the effects of CMOS technology scaling on the high temperature characteristics (from 25/spl deg/C to 125/spl deg/C) of the four components of off-state drain leakage (I/sub off/) (i.e. subthreshold leakage (I/sub sub/),
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b6e47d2401bbee217c07431b58032d2f
https://doi.org/10.1109/ted.2002.1003727
https://doi.org/10.1109/ted.2002.1003727
Autor:
Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, George H. Chang, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Sreedhar Natarajan, Jonathan Chang
Publikováno v:
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::73a2f3c01158a98a42cc5905dc1cc115
https://doi.org/10.1109/isscc.2014.6757416
https://doi.org/10.1109/isscc.2014.6757416