Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Jhnanesh Somayaji"'
Publikováno v:
2022 IEEE International Conference on Emerging Electronics (ICEE).
Publikováno v:
2022 IEEE International Conference on Emerging Electronics (ICEE).
Publikováno v:
2022 IEEE International Conference on Emerging Electronics (ICEE).
Publikováno v:
IEEE Transactions on Electron Devices. 67:4728-4735
This article explores the scope of drain-extended FinFET (DeFinFET) as a high-voltage (HV) device contender for Fin-based SoC applications. For the first time, guidelines for efficient and reliable HV integration in sub-14 nm FinFET nodes are given.
Publikováno v:
2020 5th IEEE International Conference on Emerging Electronics (ICEE).
Publikováno v:
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
In this paper, we present the impact of Superjunction (SJ) implant on the performance challenges encountered by LDMOS in the ONstate while developing insights into Space Charge Modulation (SCM) and Quasi-Saturation (QS) behavior in these devices. SJ-
Autor:
B. Jhnanesh Somayaji, M. S. Bhat
Publikováno v:
Journal of Low Power Electronics. 13:669-677
Publikováno v:
IEEE Transactions on Electron Devices. 64:4175-4183
Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed while keeping only performance targets for a given application in mind. In this paper, for the first time, performance and reliability codesign approach usin
Autor:
M. S. Bhat, B. Jhnanesh Somayaji
Publikováno v:
ISED
This paper presents the design of RESURF based non-conventional LDMOS and its parametric analysis. The work investigates the impact of three primary parameters relating to p-implant, namely implant placement distance, implant doping and implant thick
Conference
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