Zobrazeno 1 - 10
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pro vyhledávání: '"Jha, Chandan Kumar"'
Autor:
Singh, Simranjeet, Bende, Ankit, Jha, Chandan Kumar, Rana, Vikas, Drechsler, Rolf, Patkar, Sachin, Merchant, Farhad
In-memory computing (IMC) has gained significant attention recently as it attempts to reduce the impact of memory bottlenecks. Numerous schemes for digital IMC are presented in the literature, focusing on logic operations. Often, an application's des
Externí odkaz:
http://arxiv.org/abs/2407.02921
Autor:
Bende, Ankit, Singh, Simranjeet, Jha, Chandan Kumar, Kempen, Tim, Cüppers, Felix, Bengel, Christopher, Zambanini, Andre, Nielinger, Dennis, Patkar, Sachin, Drechsler, Rolf, Waser, Rainer, Merchant, Farhad, Rana, Vikas
Memristor-aided logic (MAGIC) design style holds a high promise for realizing digital logic-in-memory functionality. The ability to implement a specific gate in a MAGIC design style hinges on the SET-to-RESET threshold ratio. The TaOx memristive devi
Externí odkaz:
http://arxiv.org/abs/2310.10460
Autor:
Singh, Simranjeet, Jha, Chandan Kumar, Bende, Ankit, Rana, Vikas, Patkar, Sachin, Drechsler, Rolf, Merchant, Farhad
Existing logic-in-memory (LiM) research is limited to generating mappings and micro-operations. In this paper, we present~\emph{MemSPICE}, a novel framework that addresses this gap by automatically generating both the netlist and testbench needed to
Externí odkaz:
http://arxiv.org/abs/2309.04868
Autor:
Singh, Simranjeet, Jha, Chandan Kumar, Bende, Ankit, Thangkhiew, Phrangboklang Lyngton, Rana, Vikas, Patkar, Sachin, Drechsler, Rolf, Merchant, Farhad
Memristor-based logic-in-memory (LiM) has become popular as a means to overcome the von Neumann bottleneck in traditional data-intensive computing. Recently, the memristor-aided logic (MAGIC) design style has gained immense traction for LiM due to it
Externí odkaz:
http://arxiv.org/abs/2307.03669
Autor:
Singh, Simranjeet, Ghazal, Omar, Jha, Chandan Kumar, Rana, Vikas, Drechsler, Rolf, Shafik, Rishad, Yakovlev, Alex, Patkar, Sachin, Merchant, Farhad
Data movement costs constitute a significant bottleneck in modern machine learning (ML) systems. When combined with the computational complexity of algorithms, such as neural networks, designing hardware accelerators with low energy footprint remains
Externí odkaz:
http://arxiv.org/abs/2304.13552
Autor:
Jha, Chandan Kumar, author, Sachan, Amit, author
Publikováno v:
Fostering Sustainable Development in the Age of Technologies
Traditional computers with von Neumann architecture are unable to meet the latency and scalability challenges of Deep Neural Network (DNN) workloads. Various DNN accelerators based on Conventional compute Hardware Accelerator (CHA), Near-Data-Process
Externí odkaz:
http://arxiv.org/abs/2208.05294
Autor:
Jha, Nitya1 jhanitya629@gmail.com, Jha, Chandan Kumar2
Publikováno v:
Asian Journal of Medical Sciences. Jul2024, Vol. 15 Issue 7, p39-44. 6p.
Publikováno v:
In Economic Modelling July 2024 136