Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Jerome Teysseyre"'
Publikováno v:
2016 IEEE 66th Electronic Components and Technology Conference (ECTC).
Board-level thermal cycling reliability performance of two buckets of discrete power packages is evaluated by both Finite Element Analysis (FEA) and an actual test. One bucket consists of smaller size packages and the other consists of bigger size pa
Autor:
Pandi C. Marimuthu, Yaojian Lin, Xavier Baraton, Yonggang Jin, Jerome Teysseyre, Seung Wook Yoon
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2012:001507-001526
Current and future demands of mobile/portable electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions w
Publikováno v:
2015 16th International Conference on Electronic Packaging Technology (ICEPT).
In this paper, a 3-D finite element (FE) model was established to simulate the dynamic vibration in lead frame of molded leaded package (MLP during wire bonding process. The dynamic vibration response in the MLP will be examined. Four lead frame desi
Publikováno v:
Materials Science and Engineering: B. 83:158-164
We report on the effects of hydrothermal ageing on the dielectric properties of epoxy-silica composites used for microelectronic packaging. The study was carried out for samples with various degrees of curing. Epoxy compounds were subjected to moistu
Publikováno v:
Journal of Materials Science: Materials in Electronics. 12:81-86
We studied the dielectric properties (dielectric constant and loss factor) of epoxy molding compounds used for electronic packaging, as a function of frequency (100 Hz–100 kHz) and temperature (25–100 °C). Studies were performed for samples with
Publikováno v:
2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).
System-in-Package (SiP) which combines different chips and technologies into a single package is a viable solution to meet the rigorous requirements for today's mixed signal system integration. As the level of integration increases, challenges relate
Autor:
Seung Wook Yoon, Yonggang Jin, Xavier Baraton, Jerome Teysseyre, Pandi C. Marimuthu, Yaojian Lin
Publikováno v:
2012 IEEE 62nd Electronic Components and Technology Conference.
The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires fan-out packaging, where the package size is larger than the chip
Publikováno v:
2011 IEEE 13th Electronics Packaging Technology Conference.
In this paper, we will compare Cu wire and Au wire behavior during pull test and package reliability test through thermo-mechanical simulation. Relationship between wire pull test and package reliability test, i.e. thermal cycling, is also evaluated
Publikováno v:
Proc.7th Electronics Packaging Technology Conference (EPTC 2005)
Proc.7th Electronics Packaging Technology Conference (EPTC 2005), 2005, Singapore
Scopus-Elsevier
Proc.7th Electronics Packaging Technology Conference (EPTC 2005), 2005, Singapore
Scopus-Elsevier
In this work, we present the potentialities of the surface potential method to investigate electrostatics charges deposited on epoxy resins used in packaging. Curing and post-mould-curing (PMC), with various durations have been performed on epoxy res
Autor:
Fong Kuan Ng, Jerome Teysseyre, Say Chye Joachim Loo, Tong Yan Tee, Xueren Zhang, Subodh Mhaisalkar, Xinyu Du, Wenhui Zhu, Hun Shen Ng, Chwee Teck Lim, S. Chew, E. Bool
Publikováno v:
Scopus-Elsevier
Package reliability is a great concern in developing new advanced packages. This paper presents some of the modeling and testing activities for the design of mixed flip-chip (FC)-wire bond (WB) stacked die BGA module with molded underfill (MUF). The