Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Jeroen Van Borkulo"'
Autor:
Aakrati Jain, Kamal Sikka, Shidong Li, Juan-Manuel Gomez, Marc Bergendahl, Spyridon Skordas, Jeroen Van Borkulo, Roman Doll, Kees Biesheuvel, Mark Mueller
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Autor:
Mark Christian Mueller, Jeroen van Borkulo, Kees Biesheuvel, Roman Doll, Dishit P. Parekh, Juan-Manuel Gomez, Kamal K. Sikka, Aakrati Jain, Marc A. Bergendahl
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
The recently introduced Direct Bonded Heterogeneous Integration (DBHi) Si bridge technology has chips connected by a bridge housed inside a cavity or trench that is precisely machined in the chip-carrier laminate. The size, thickness, and placement c
Publikováno v:
2020 China Semiconductor Technology International Conference (CSTIC).
Over the last years, singulation of thin semiconductor wafers with (ultra) low-K top layer has become a challenge in the production process of integrated circuits. The traditional blade dicing process is encountering serious yield issues. These issue
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
As the materials that the wafer dicing process need to singulate become more complex a diverging current Process of Record (PoR) dicing technologies are not able to meet the quality and or cost requirements. Laser provides the solution to dice all th
Publikováno v:
2019 China Semiconductor Technology International Conference (CSTIC).
It is a main stream for 3-dimensional (3D) NAND flash which has the advantage of large storage capacity, excellent and reliable performance. Several different wafer architectures for 3D NAND flash including BICS (Bit Cost Scalable), TACT (Terabit Cel
Publikováno v:
2018 IEEE 68th Electronic Components and Technology Conference (ECTC).
Over the last years, singulation of thin semiconductor wafers with (ultra) low-K top layer has become a challenge in the production process of integrated circuits. The traditional blade dicing process is encountering serious yield issues. These issue
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2015:001446-001474
The ongoing trend to thinner wafers which are needed for continuous miniaturization, 3D packaging and IC performance, inevitably means that sole blade dicing evolution is coming to an end. Over the last years several technologies to handle the separa
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
The introduction of Chip Scale Package (CSP) has become one of the key packaging solutions in the recent semiconductor industry. With the advantages of reducing the package size and stacking capability for higher interconnects, CSP's are continuously
Publikováno v:
2016 IEEE 18th Electronics Packaging Technology Conference (EPTC).
The introduction of Chip Scale Package (CSP) has become one of the key packaging solutions in the recent semiconductor industry. With the advantages of reducing the package size and stacking capability for higher interconnects, CSP's are continuously
Publikováno v:
International Symposium on Microelectronics. 2013:000564-000568
Over the years the singulation of semiconductor wafers with a low-κ top structures has become a challenge in the production process of integrated circuits. With the traditional blade dicing process serious yield issues are encountered. These problem