Zobrazeno 1 - 10
of 16
pro vyhledávání: '"Jeongsup Lee"'
Publikováno v:
IEEE Solid-State Circuits Letters. 3:130-133
This letter proposes a robust synchronous wide-range clocked level converter (LC) that converts subthreshold input signals to high I/O voltages for ultra-low power (ULP) SoCs. By biasing the circuit using nMOS leakage current, the design offers robus
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f5c442846031b25c90d131277d62b4ce
https://doi.org/10.1109/lssc.2020.3007875
https://doi.org/10.1109/lssc.2020.3007875
Autor:
Mehdi Saligane, Yiqun Zhang, Yejoong Kim, Satoru Miyoshi, David Blaauw, Masaru Kawaminami, Jeongsup Lee, Dennis Sylvester, Seokhyeon Jeong, Jongyup Lim, Wootaek Lim, Qing Dong, Makoto Yasuda
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:87-97
Energy-optimal operation is one of the key requirements of the Internet-of-Things (IoT) applications to increase battery life. In this article, using a combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB), the energy-optimal o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cc843412180571b6dfa4a4c72dcae4bd
https://doi.org/10.1109/jssc.2019.2939890
https://doi.org/10.1109/jssc.2019.2939890
Publikováno v:
CICC
Edge devices are essential elements for Internet of Things (1oT). To extend the battery life or achieve batteryless operation through energy harvesting, low power consumption is one of the key challenges for low-power edge devices. For emerging appli
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::555770000b70841ecc8cebe5351a2ded
https://doi.org/10.1109/cicc51472.2021.9431508
https://doi.org/10.1109/cicc51472.2021.9431508
Autor:
Wenbo Duan, Morteza Fayazi, Ronald G. Dreslinski, Kyumin Kwon, Sumanth Kamineni, Jeongsup Lee, Chien-Hen Chen, Dennis Sylvester, Benton H. Calhoun, Mehdi Saligane, David D. Wentzloff, David Blaauw, Yaswanth K. Cherivirala, Tutu Ajayi, Shourya Gupta
Publikováno v:
VLSI-SoC: Design Trends ISBN: 9783030816407
VLSI-SoC (Selected Papers)
VLSI-SoC (Selected Papers)
This chapter presents the world’s first autonomous mixed-signal SoC framework, driven entirely by user constraints, along with a suite of automated generators for analog blocks. The process-agnostic framework takes high-level user intent as inputs
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce1fd6cac2ce8ed5252c6a70d983d76c
https://doi.org/10.1007/978-3-030-81641-4_4
https://doi.org/10.1007/978-3-030-81641-4_4
Autor:
Taehun Yoon, Sangeun Lee, Hyo Sup Won, Taeho Kim, Jinho Han, Jin-Hee Lee, Joon-Yeong Lee, Hyeon-Min Bae, Kwangseok Han, Jinho Park, Jeongsup Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 52:688-703
This paper presents the first 103.125-Gb/s multilink gearbox (MLG) IC, which facilitates the transport of independent 10and 40-GbE signals to 4 × 25.78 Gb/s physical layers, such as 100GBASE-xR4. The IC consumes only 1.37 W while implementing compli
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::602a5bd61f852d9abc73e7263d4a0100
https://doi.org/10.1109/jssc.2016.2636858
https://doi.org/10.1109/jssc.2016.2636858
Autor:
Bangqi Xu, Vidya A. Chhabria, Marina Neseem, Tutu Ajayi, Abdelrahman Hosny, Sherief Reda, Soheil Hashemi, Min-Soo Kim, Jeongsup Lee, Mateus Fogaca, Mingyu Woo, Mehdi Saligane, Andrew B. Kahng, Lutong Wang, Mohamed Shalan, Geraldo Pradipta, Carl Sechen, Zhehong Wang, Sachin S. Sapatnekar, Uday Mallappa, William Swartz
Publikováno v:
DAC
We describe the planned Alpha release of OpenROAD, an open-source end-to-end silicon compiler. OpenROAD will help realize the goal of "democratization of hardware design", by reducing cost, expertise, schedule and risk barriers that confront system d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87dc3ca80acf5db3c63a7cf038340058
https://doi.org/10.1145/3316781.3326334
https://doi.org/10.1145/3316781.3326334
Autor:
Yejoong Kim, Jeongsup Lee, Yiqun Zhang, Qing Dong, Dennis Sylvester, Masaru Kawaminami, Makoto Yasuda, Mehdi Saligane, Jongyup Lim, Satoru Miyoshi, David Blaauw, Seokhyeon Jeong, Wooteak Lim
Publikováno v:
ISSCC
Wireless sensors for IoT applications have become a prominent computing class and are typically severely power constrained. IoT devices are deployed in a wide range of environments and low power consumption must be guaranteed across a wide temperatur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::04bcbbab7d36bea1aec6bfba54539077
https://doi.org/10.1109/isscc.2019.8662454
https://doi.org/10.1109/isscc.2019.8662454
Autor:
Jeongsup Lee, Taehun Yoon, Hyeon-Min Bae, Kwangseok Han, Sangeun Lee, Joon-Yeong Lee, Taeho Kim, Jinho Park
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:2475-2484
A phase interpolator (PI)-based $10\times 10$ Gb/s bootstrap transceiver for referenceless and lane-independent operation is presented. PI output clock signals phase locked to the input data are used as reference clock signals for frequency locking t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::399f34e6d953a1d154ed7de347fac131
https://doi.org/10.1109/jssc.2016.2590550
https://doi.org/10.1109/jssc.2016.2590550
Autor:
Soon-Won Kwon, Taeho Kim, Hyeon-Min Bae, Kwangseok Han, Sangeun Lee, Taehun Yoon, Joon-Yeong Lee, Jinho Park, Jin-Hee Lee, Hyosup Won, Jeongsup Lee
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:2817-2828
An automatic loop gain control algorithm (ALGC) for a bang-bang (BB) clock and data recovery (CDR) is proposed. The proposed algorithm finds the optimum loop gain using the autocorrelation of a BBPD output signal for minimum MSE performance. Mathemat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aced0c0f83f8df5fa10d7810351b92da
https://doi.org/10.1109/tcsi.2015.2495725
https://doi.org/10.1109/tcsi.2015.2495725
Autor:
Supreet Jeloka, David Blaauw, Jeongsup Lee, Qing Dong, Jinal Shah, Ziyun Li, Dennis Sylvester, Kaiyuan Yang
Publikováno v:
2017 Symposium on VLSI Circuits.
Embedded flash for low power sensing systems require very low write energy and peak power. This work proposes a 130nm, 1024×260 SONOS flash with an ultra-wide 1Kb program cycle, using efficient FN tunneling based programing and a dedicated, multi-ou
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2df42cedce99df9bd8eb74b96a80fc15
https://doi.org/10.23919/vlsic.2017.8008480
https://doi.org/10.23919/vlsic.2017.8008480