A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip

Autor: Hoi-Jun Yoo, Jeonghoon Kook, Chi-Weon Yoon, Se-Joong Lee, Ramchan Woo

Publikováno v: IEEE Journal of Solid-State Circuits. 37:1352-1355

A low-power three-dimensional (3-D) rendering engine is implemented as part of a mobile personal digital assistant (PDA) chip. Six-megabit embedded DRAM macros attached to 8-pixel-parallel rendering logic are logically localized with a 3.2-GB/s runti

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7debb2ea95332504cbd5f5206f9c8085
https://doi.org/10.1109/jssc.2002.803051

Embedded DRAM (eDRAM) power-energy estimation for system-on-a-chip (SoC) applications.

Autor: Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo

Publikováno v: Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia & South Pacific Design Automation Conference & 15h International Conference on VLSI Design; 2002, p625-630, 6p

A 120 mW embedded 3D graphics rendering engine with 6 Mb logically local frame-buffer and 3.2 GByte/s run-time reconfigurable bus for PDA-chip.

Autor: Ramchan Woo, Chi-Weon Yoon, Jeonghoon Kook, Se-Joong Lee, Kangmin Lee, Yong-Ha Park, Hoi-Jun Yoo

Publikováno v: 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185); 2001, p95-98, 4p

A 120 mW embedded 3D graphics rendering engine with 6 Mb logically local frame-buffer and 3.2 GByte/s run-time reconfigurable bus for PDA-chip

Autor: Chi-Weon Yoon, Hoi-Jun Yoo, Kangmin Lee, Ramchan Woo, Jeonghoon Kook, Yong-Ha Park, Se-Joong Lee

Publikováno v: 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

An embedded 3D graphics rendering engine (E3GRE) is implemented as a part of a mobile PDA-chip. 6 Mb embedded DRAM (eDRAM) macros attached to 8-pixel-parallel rendering logic are logically localized with 3.2 GByte/s runtime reconfigurable bus, by whi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f35a4317be542474d5535580741dd249
https://doi.org/10.1109/vlsic.2001.934206

A 80/20 MHz 160 mW multimedia processor integrated with embedded DRAM MPEG-4 accelerator and 3D rendering engine for mobile applications

Autor: null Chi-Weon Yoon, R. Woo, null Jeonghoon Kook, null Se-Joong Lee, null Langmin Lee, null Young-Don Bae, null In-Cheol Park, null Hoi-Jun Yoo

Publikováno v: 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0a5167c6c271282c2a780a5ea75f2170
https://doi.org/10.1109/isscc.2001.912578