Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Jente Benedict Kuang"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:597-604
We present a dynamic body charge modulation technique to improve the matching of CMOS device threshold voltage (V/sub t/) characteristics in the partially depleted silicon-on-insulator (SOI) technology. For a latch-type sense amplifier in the SRAM co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::04355c808a4b2d916c4aab8bcad0f2f9
https://doi.org/10.1109/4.913737
https://doi.org/10.1109/4.913737
Autor:
Carl J. Anderson, Lawrence F. Wagner, Ching-Te Chuang, Jin Ji, Chang-Ming Hsieh, Pong-Fei Lu, Jente Benedict Kuang, Shao-Fu S. Chu, L. Hsu, Mario M. Pelella
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:1241-1253
This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dyna
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66882935c1fc7847ebba2f7c64ae968d
https://doi.org/10.1109/4.604080
https://doi.org/10.1109/4.604080
Autor:
Asen Asenov, Campbell Millar, C. Alexander, Xingsheng Wang, Binjie Cheng, Jente Benedict Kuang, D. Reid, Sani R. Nassif, Andrew R. Brown
Publikováno v:
2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
This paper presents a principal component analysis (PCA)-based unified compact modelling strategy for process-induced and statistical variability in 14-nm double gate SOI FinFET technology. There is strong interplay between process and statistical va
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a66557adff0fc0ea692a88dc67ce57cc
https://doi.org/10.1109/sispad.2013.6650594
https://doi.org/10.1109/sispad.2013.6650594
Autor:
Asen Asenov, Binjie Cheng, Jente Benedict Kuang, Xingsheng Wang, Andrew R. Brown, D. Reid, Campbell Millar, Sani R. Nassif
Publikováno v:
ISCAS
We report a systematic study on the impact of process and statistical variability on SRAM design in a 14nm SOI FinFET technology node. A comprehensive statistical compact modelling strategy is developed for the early delivery of reliable PDK model, w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::774fb51f38ea8e71b9a230e7ae16eec1
https://doi.org/10.1109/iscas.2013.6572347
https://doi.org/10.1109/iscas.2013.6572347
Publikováno v:
2005 IEEE International SOI Conference Proceedings.
In this paper, conditional keeper, charge sharing prevention, and clock load reduction techniques for symmetrical and asymmetrical DG devices have been presented. Performance benefit, noise immunity, area and power efficiency can be achieved when tec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92fb18ecbeaf5a14d1176c5076d91d18
https://doi.org/10.1109/soi.2005.1563539
https://doi.org/10.1109/soi.2005.1563539
Autor:
Jacob A. Abraham, Chandler Todd McDowell, Kevin J. Nowka, Jente Benedict Kuang, R. K. Montoye, Hung Ngo, Wendy A. Belluomini, R. Datta
Publikováno v:
ISCAS (2)
This paper presents a 4-to-2 Carry Save Adder (CSA) using dynamic logic and the Limited Switch Dynamic Logic (LSDL) circuit family. Adders are a crucial portion of all floating-point units, since they form the base element of all arithmetic functions
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f8aae8427c54253bb5aa18f226a0af53
https://doi.org/10.1109/iscas.2004.1329312
https://doi.org/10.1109/iscas.2004.1329312
Publikováno v:
1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345).
It has been reported (Kuang et al., 1997; Lu et al., 1997) that SOI passgate circuits suffer history effects and adverse initial-cycle parasitic bipolar currents, which cause difficulties in circuit timing and limit direct design reuse from original
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::65a2854fd7e05d01117e0376023a31e7
https://doi.org/10.1109/soi.1999.819861
https://doi.org/10.1109/soi.1999.819861
Publikováno v:
2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).
In this paper, we present a low-cell-stress latch-type sensing system, which seeks to bias the bit lines low as frequently as possible to relieve voltage stress on the access transistor for improved cell stability and yield while maintaining high per
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ad276820b479d617938364ec2ae1e100
https://doi.org/10.1109/soic.2001.958003
https://doi.org/10.1109/soic.2001.958003
Autor:
Jente Benedict Kuang, C.T. Chuang
Publikováno v:
2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207).
We present a tri-state dynamic body charge modulation technique for sense and differential amplifiers in SOI technology. To execute a RAM read function, sensing devices are designed to cycle through three distinctive (i.e., high body bias, floating b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0bc9f76ee75e3b16ff6ee90cc2f5f592
https://doi.org/10.1109/soic.2001.958023
https://doi.org/10.1109/soic.2001.958023
Publikováno v:
2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).
Dynamic CMOS SOI sensing circuits are prone to performance variation and mismatch in transfer characteristics (Kuang et al, 1997; Allen et al, 1999) as a result of hysteretic body potential and V/sub t/ differences. In dual-railed RAM and register fi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cd10e4816fc2078980d9fb4cc765d502
https://doi.org/10.1109/soi.2000.892789
https://doi.org/10.1109/soi.2000.892789