Výsledky vyhledávání - "Jente B. Kuang"

TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

Autor: Bryan L. Jackson, Rajit Manohar, Andrew S. Cassidy, Brian Taba, Gi-Joon Nam, Paul A. Merolla, Rodrigo Alvarez-Icaza, William P. Risk, Jente B. Kuang, Pallab Datta, Filipp Akopyan, Michael P. Beakes, John V. Arthur, Nabil Imam, Bernard Brezzo, Yutaka Nakamura, Dharmendra S. Modha, Jun Sawada

Publikováno v: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 34:1537-1557

The new era of cognitive computing brings forth the grand challenge of developing systems capable of processing massive amounts of noisy multisensory data. This type of intelligent computing poses a set of constraints, including real-time operation,

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c4608c0c8298c2492f7d58bbe0cd2a77
https://doi.org/10.1109/tcad.2015.2474396

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Variability Aware Simulation Based Design- Technology Cooptimization (DTCO) Flow in 14 nm FinFET/SRAM Cooptimization

Autor: Craig Alexander, Campbell Millar, Xingsheng Wang, Binjie Cheng, Sani R. Nassif, Jente B. Kuang, Andrew R. Brown, Salvatore Maria Amoroso, Asen Asenov

Publikováno v: IEEE Transactions on Electron Devices. 62:1682-1690

In this paper, we use an automated tool flow in a 14 nm CMOS fin-shaped field-effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statist

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8f3acb35f16478f66a01660413e03b41
https://doi.org/10.1109/ted.2014.2363117

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Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology

Autor: Xingsheng Wang, Binjie Cheng, Jente B. Kuang, Sani Nassif, Andrew R. Brown, Campbell Millar, Asen Asenov

Publikováno v: IEEE Design & Test. 30:18-28

This paper presents an evaluation of 14-nm SOI FinFET CMOS SRAM codesign techniques in the presence of statistical variability and reliability impact. As statistical variability sources random discrete dopants, gate-edge roughness, fi-edge roughness,

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::38f0213dd8ede687822972e60e93ac9b
https://doi.org/10.1109/mdat.2013.2266395

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Interplay Between Process-Induced and Statistical Variability in 14-nm CMOS Technology Double-Gate SOI FinFETs

Autor: Xingsheng Wang, Campbell Millar, Jente B. Kuang, Asen Asenov, Binjie Cheng, Andrew R. Brown, Sani R. Nassif

Publikováno v: IEEE Transactions on Electron Devices. 60:2485-2492

This paper presents a comprehensive simulation study of the interactions between long-range process and short-range statistical variability in a 14-nm technology node silicon-on-insulator FinFET. First, the individual and combined impact of the relev

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::546962a0170e4aa62b78151532c949e3
https://doi.org/10.1109/ted.2013.2267745

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A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

Publikováno v: IEEE Journal of Solid-State Circuits. 44:1216-1226

We describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation , a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f68712ec5bfaf69d78fe5b66dec9430d
https://doi.org/10.1109/jssc.2009.2014207

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Design Considerations for PD/SOI SRAM: Impact of Gate Leakage and Threshold Voltage Variation

Autor: Jente B. Kuang, Jayakumaran Sivagnaname, Sani R. Nassif, Rajiv V. Joshi, Tuyet Y. Nguyen, Dhruva Acharyya, Rouwaida Kanj

Publikováno v: IEEE Transactions on Semiconductor Manufacturing. 21:33-40

We present a critical study of the impact of gate tunneling currents on the yield of 65-nm partially depleted/silicon-on-insulator (PD/SOI) SRAM designs. A new gate leakage monitor structure is developed to obtain device-specific gate leakage charact

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2641a0cd86d77ba5846822b1d5edf143
https://doi.org/10.1109/tsm.2007.913189

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A floating-body charge monitoring technique for partially depleted SOI technology

Autor: Ching-Te Chuang, Jente B. Kuang, M. J. Saccamango, S. Ratanaphanyarat

Publikováno v: International Journal of Electronics. 91:625-637

This paper presents a floating-body charge monitoring technique, which does not require the use of body contacts on the device being monitored. A charge monitor is placed along side with the circuit that is susceptible to the floating-body effects in

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9f71320ba222f584f5917c0e350f5a21
https://doi.org/10.1080/00207210412331332961

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SRAM bitline circuits on PD SOI: advantages and concerns

Autor: Shao-Fu S. Chu, Somnuk Ratanaphanyarat, Roy Childs Flaker, Jente B. Kuang, G.G. Shahidi, Lawrence F. Wagner, L. Hsu, M.J. Saccamango

Publikováno v: IEEE Journal of Solid-State Circuits. 32:837-844

This paper presents a study of sub-0.25-/spl mu/m CMOS SRAM bitline circuitry on partially depleted (PD) silicon-on-insulator (SOI) technology. SOI implementations outperform conventional bulk ones due to significant reduction of collective device ju

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::43fcbf776f2ac1f6eaa108802df146f5
https://doi.org/10.1109/4.585285

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Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability

Autor: Xingsheng Wang, Campbell Millar, Sani R. Nassif, Jente B. Kuang, Asen Asenov, Binjie Cheng, Andrew R. Brown

Publikováno v: ESSDERC

Variability is a critical concern for the stability and yield of SRAM with minimized size. We present a study of a 14 nm node SOI FinFET SRAM cell under the influence of statistical variability and random charge trapping due to positive/negative bias

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b916273557808a85e04c8a8b2b9de637
https://doi.org/10.1109/essderc.2013.6818862

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Statistical yield analysis of silicon-on-insulator embedded DRAM

Autor: M. Meterelliyoz, William Robert Reohr, Rajiv V. Joshi, Rouwaida Kanj, Jae-Joon Kim, Kevin J. Nowka, Jente B. Kuang, Sani R. Nassif

Publikováno v: ISQED

We study the yield of a 65nm SOI eDRAM design. The impact of random dopant fluctuations in the cell and micro sense amp is studied under different systematic corner and device type considerations. Trench capacitor variation effects and yield timing w

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2829fed904c62258d0f28e1666439390
https://doi.org/10.1109/isqed.2009.4810292

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