Zobrazeno 1 - 10
of 70
pro vyhledávání: '"Jennifer Dworak"'
Publikováno v:
Journal of Electronic Testing.
Test sets that target standard fault models may not always be sufficient for detecting all defects. To evaluate test sets for the detection of unmodeled defects, n-detect test sets (which detect all modeled faults at least n times) have previously be
Autor:
Kundan Nepal, Jennifer Dworak, Alfred L. Crouch, Soha Alhelaly, Ping Gui, Theodore W. Manikas
Publikováno v:
IEEE Transactions on Emerging Topics in Computing. 9:774-786
3D integrated circuits introduce both advantages and disadvantages for security. Among the disadvantages unique to 3D is the potential insertion of a Trojan die into the stack between two legitimate dies. Such a die could be used to snoop information
Publikováno v:
2022 IEEE 31st Microelectronics Design & Test Symposium (MDTS).
Publikováno v:
IEEE Design & Test. 37:14-20
During scan shift, high simultaneous toggling of sequential logic on a System-on-Chip (SoC) can result in increased Power Supply Noise (PSN). The problem gets exacerbated when the switching logic is present in neighboring blocks on the SoC that share
Autor:
Kundan Nepal, Jennifer Dworak, Fanchen Zhang, Theodore W. Manikas, Hui Jiang, Yi Sun, R. Iris Bahar
Publikováno v:
Journal of Electronic Testing. 35:887-900
We propose an architecture for a Field Programmable Gate Array (FPGA) based tester for a 3D stacked integrated circuit (IC). Due to the very short distances between dies in a stack that can make SerDes connections very efficient and the high density
Autor:
Jennifer Dworak, David Brauchler
Publikováno v:
ITC
Embedded instruments are responsible for aiding in a wide range of tasks engineers must perform on integrated circuits (ICs), including testing, debugging, and analysis. The IEEE 1687 IJTAG standard provides efficient access to these instruments with
Autor:
R. Iris Bahar, Yi Sun, Theodore W. Manikas, Matan Segal, Jennifer Dworak, Lakshmi Ramakrishnan, Kundan Nepal, Hui Jiang
Publikováno v:
ICECS
Excessive power during in–field testing can cause multiple issues, including invalidation of the test results, over- heating, and damage to the circuit. In this paper, we evaluate the reduction of capture power when specific segments of a scan chai
Publikováno v:
VTS
During scan shift, high simultaneous toggling of sequential logic on a System-on-Chip (SoC) can result in increased Power Supply Noise (PSN). The problem gets exacerbated when the switching logic is present in neighboring blocks on the SoC that share
Autor:
Peilin Song, Daniel W. Engels, Yuhe Xia, Jennifer Dworak, Ping Gui, Gary A. Evans, Chi Zhang, Alfred L. Crouch, Lakshmi Ramakrishnan, Peter L. Levin, Franco Stellari, Saurabh Gupta, Scott McWilliams, Naigang Wang
Publikováno v:
VTS
The term CyberSecurity means many different things to many people - some think of data security, some think of identity protection, some think of intrusion attacks on the internet or USB ports. In reality, CyberSecurity represents any type of attack