Zobrazeno 1 - 10
of 27
pro vyhledávání: '"Jengyi Yu"'
Autor:
Mohammed Alvi, Richard Gottscho, Ali Haider, Seongjun Heo, PingYen Hsieh, Ching-Chung Huang, Gosia Jurczak, Benjamin Kam, Ji Yeon Kim, Billie Li, Da Li, Henry Nguyen, Yang Pan, Daniel Peter, Nader Shamma, Anuja De Silva, Samantha Tan, Ethen Wang, Timothy Weidman, Rich Wise, Morrey Wu, Elisseos Verveniotis, Boris Volosskiy, Jengyi Yu, Hicham Zaid
Publikováno v:
Advances in Patterning Materials and Processes XXXIX.
Publikováno v:
Advanced Etch Technology for Nanopatterning VIII.
Despite the innumerable advances in EUV lithography for materials, optics, and process in recent years, the N7 and N5 targets for resolution, line roughness, and sensitivity (RLS, collectively) have not simultaneously been achieved from both a yield
Autor:
Sanjay Gopinath, Yunlong Li, Gerald Beyer, Daniela M. Anjos, Philippe Roussel, Jengyi Yu, Eric Beyne, Mohand Brouri, Matthew S. Thorum, Kristof Croes, Stefaan Van Huylenbroeck
Publikováno v:
Microelectronic Engineering. 156:37-40
In high aspect ratio through silicon vias (TSV's), the trench step coverage (conformality) of liner, barrier and seed is critical for both the process integration and reliability. If the conformality of a deposition process is improved, the required
Autor:
Nader Shamma, Chris Mack, Justin Jiang, Rich Wise, Liu Yang, Andrew Liang, Jengyi Yu, Liang Chen-Wei, Diane J. Hymes, Stephen M. Sirard
Publikováno v:
Metrology, Inspection, and Process Control for Microlithography XXXII.
Edge placement error (EPE) has become an increasingly critical metric to enable Moore’s Law scaling. Stochastic variations, as characterized for lines by line width roughness (LWR) and line edge roughness (LER), are dominant factors in EPE and know
Autor:
Akhil Singhal, Timothy Tran, Samantha Tan, Liang Chen-Wei, Girish Dixit, David Rio, Nader Shamma, Bart van Schravendijk, Jelle Vandereyken, Rich Wise, Mircea Dusa, Andrew Liang, Katja Viatkina, Steven Chuang, Greg Harm, Brandon Ward, Michael Kubis, Jan Hermans, Jengyi Yu, Sirish Reddy
Publikováno v:
SPIE Proceedings.
Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires
Publikováno v:
Proceedings of SPIE; 2/16/2019, Vol. 10984, p1-9, 9p
Autor:
Joe Richardson, Mohand Brouri, Praveen Nalla, Joeri De Vos, Michele Stucchi, Sanjay Gopinath, Jengyi Yu, Gerald Beyer, Eric Beyne, Matthew S. Thorum, Stefaan Van Huylenbroeck, L. Bogaerts, Yunlong Li
Publikováno v:
3DIC
An advanced TSV metallization scheme, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling is presented. Because of the high conformality of the WN barrier and
Autor:
Jengyi Yu, Larry Schloss, Greg Harm, Daniela M. Anjos, Prashant Meshram, Praveen Nalla, Joe Richardson, Sanjay Gopinath, Tom Mountsier, Matthew S. Thorum
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
Innovative solutions have been developed to address the challenges of through-silicon via (TSV) metallization with small sizes and high aspect ratios. We demonstrate an advanced metallization scheme including conformal film depositions of metal barri
An alternative approach to backside via reveal (BVR) for a via-middle through-Silicon via (TSV) flow
Autor:
Stefan Detterbeck, Lai Wei, Joe Richardson, CheePing Lee, Tom Mountsier, Qing Xu, Prashant Meshram, Sanjay Gopinath, Jengyi Yu, Praveen Nalla, Matthew S. Thorum
Publikováno v:
2015 IEEE 65th Electronic Components and Technology Conference (ECTC).
An alternative scheme has been developed to combine three major backside via reveal (BVR) processes, including (a) wafer polishing, (b) Si recess etching, and (c) wet clean, into an integrated wet etch process to replace the high cost chemical-mechan
Autor:
Yunlong Li, Praveen Nalla, Sanjay Gopinath, Jengyi Yu, Stefaan Van Huylenbroeck, Mohand Brouri, Eric Beyne, Kristof Croes, Daniela M. Anjos, Prashant Meshram, Gerald Beyer, Nancy Heylen, Matthew S. Thorum
Publikováno v:
2015 IEEE 65th Electronic Components and Technology Conference (ECTC).
An advanced Via-Middle TSV metallization scheme is presented, featuring a high conformal ALD oxide liner, a thermal ALD WN barrier, an electroless NiB platable seed and a high throughput copper ECD filling process. Because of the high conformality of