Zobrazeno 1 - 10
of 32
pro vyhledávání: '"Jei-Hwan Yoo"'
Autor:
Hui-jung Kim, Hyun-Gi Kim, Young-Hyun Jun, Gyo-Young Jin, Donggun Park, Jin-Young Kim, Jae-Man Yoon, Sua Kim, Ki-whan Song, Jei-Hwan Yoo, Hyun-Chul Kang, Chang-Hyun Kim, Duk-ha Park, Hwan-Wook Park, Kang-Uk Kim, Yeong-Taek Lee, Woo-Seop Kim, Nam-Kyun Tak, Kyungseok Oh, Yong Chul Oh, Hyun-Woo Chung
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:880-888
A functional 4F2 DRAM was implemented based on the technology combination of stack capacitor and surrounding-gate vertical channel access transistor (VCAT). A high performance VCAT has been developed showing excellent Ion-Ioff characteristics with mo
Autor:
Jei-Hwan Yoo, Hoe-ju Chung, Duk-Min Kwon, Woo-Seop Kim, Man-Sik Choi, Dong-Hyun Jang, Sae-Jang Oh, Jaesung Ahn, So-Ra Kim, Jung-Bae Lee, Chang-Hyun Kim, Sooho Cha, Jin-Ho Kim, Seongmoo Heo, Hyun-Kyung Kim, Hoon Lee, Nam-Seog Kim, Jae-Wook Lee, Uk-Song Kang, Han-Sung Joo, Eun-Mi Lee, Keum-Hee Ma, Tae-Kyung Jung, Soon-Hong Ahn
Publikováno v:
ISSCC
An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the
Autor:
Jei-Hwan Yoo, Woo-Seop Kim, Kim Sang-Yun, Hyung-seuk Kim, Jae-Kwan Kim, Soouk Lim, Hoe-ju Chung, Jung-Bae Lee, Moon-Sook Park, Yun-Sang Lee, Jung Sunwoo, Young-don Choi, Hwan-Wook Park, Young-Chan Jang, Chang-Hyun Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:2987-2998
A 1-Gbit DRAM with 5.8-Gb/s/pin unidirectional differential I/Os was implemented by 70 nm DRAM process and a main memory module with dual in-line memory module was assembled. The implemented DRAM chips have control methods for core noise injection an
Autor:
Sang Pyo Hong, Hongil Yoon, Dong Il Seo, Kyu Chan Lee, Hyun Seok Lee, Ki-Chul Chun, Jae-Yoon Sim, Jei Hwan Yoo
Publikováno v:
Current Applied Physics. 4:25-29
A 1.8 V low-voltage and low-power 128 Mb mobile SDRAM is designed and fabricated for hand-held, battery-operated electronic devices with a 0.15-μm CMOS technology. As an essential low-voltage circuit, a triple pumping scheme is proposed to generate
Autor:
Dong-Il Seo, Hongil Yoon, Soo-In Cho, Jei-Hwan Yoo, Sang-Pyo Hong, Ki-Chul Chun, Hyun Seok Lee, Jae-Yoon Sim, Kyu-Chan Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:631-640
To verify three important circuit schemes suitable for DRAMs in mobile applications, a 1.8-V 128-Mb SDRAM was implemented with a 0.15-/spl mu/m technology. To achieve an ideal 33% efficiency, the double boosting pump uses two capacitor's series conne
Autor:
Jai-Hoon Sim, Kyu-Chan Lee, Nam-jong Kim, Soo-In Cho, Hongil Yoon, Byung-sik Moon, Dong-ryul Ryu, Seung-Moon Yoo, Changhyun Kim, Sang-Bo Lee, Keum-Yong Kim, Jei-Hwan Yoo
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:642-648
This paper describes several new circuit design techniques for low V/sub CC/ regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (/spl Delta/V/sub BL/) as well as the V/sub GS/ margin by boosti
Autor:
Keum-Yong Kim, Ejaz Haq, Kye-Hyun Kyung, Kinam Kim, Bok-Moon Kang, Moon-Hae Son, Chang-Hyun Kim, Hyung-Kyu Lim, Soo-In Cho, K. H. Lee, Jai-Hoon Sim, Sang-Bo Lee, Jae-Gwan Park, Jong-Woo Park, Jung-Hwa Lee, Seung-Moon Yoo, Jei-Hwan Yoo, Joungho Kim, Jinman Han, Byung-sik Moon, Kang-yoon Lee, Kyu-Chan Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:1635-1644
This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an
Autor:
Jun-Ho Shin, Su-Jin Ahn, Yeong-Taek Lee, Han-Sung Joo, Jung Sunwoo, Jei-Hwan Yoo, Hoe-ju Chung, Yong-Jin Kwon, Jaehwan Kim, Beakhyoung Cho, Jae-Wook Lee, Chang-Soo Lee, Yong-Jun Lee, Mu-Hui Park, Gitae Jeong, Sang-Hoan Chang, Jin-Young Kim, Soehee Kim, Mingu Kang, Duckmin Kwon, Young-Hoon Oh, Kwang-Jin Lee, Qi Wang, Young-don Choi, Yoohwan Rho, Jae-Yun Lee, Ickhyun Song, Hideki Horii, Sooho Cha, Ki-Sung Kim
Publikováno v:
ISSCC
Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-N
Autor:
Sung-Hoon Kim, Yong-Jun Lee, Byung-Hoon Jeong, Sang-Tae Kim, Jung Sunwoo, HoGeun Cho, Jin-Young Kim, Sunghyun Jun, Inchul Shin, Hoe-ju Chung, Woo-Yeong Cho, Jae-Wook Lee, Woochul Jun, Jun-Ho Shin, Joon-Min Park, Chang-han Choi, Qi Wang, Young-don Choi, Young-Hyun Jun, Ki-whan Song, Byung-Jun Min, KiSeung Kim, Jei-Hwan Yoo, Mu-Hui Park, Yoohwan Rho, Won-Ryul Chung, Seok-Won Hwang, Sang-whan Chang, Ickhyun Song, Ki-won Lim, Beak-Hyung Cho, Kwang-Jin Lee, Sooho Cha, Jaewhan Kim, Duk-Min Kwon
Publikováno v:
ISSCC
In mobile systems, the demand for the energy saving continues to require a low power memory sub-system. During the last decade, the floating-gate flash memory has been an indispensable low power memory solution. However, NOR flash memory has begun to
Autor:
null Uksong Kang, null Hoe-Ju Chung, null Seongmoo Heo, null Soon-Hong Ahn, null Hoon Lee, null Soo-Ho Cha, null Jaesung Ahn, null DukMin Kwon, null Jin Ho Kim, null Jae-Wook Lee, null Han-Sung Joo, null Woo-Seop Kim, null Hyun-Kyung Kim, null Eun-Mi Lee, null So-Ra Kim, null Keum-Hee Ma, null Dong-Hyun Jang, null Nam-Seog Kim, null Man-Sik Choi, null Sae-Jang Oh, null Jung-Bae Lee, null Tae-Kyung Jung, null Jei-Hwan Yoo, null Changhyun Kim
Publikováno v:
2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.