Zobrazeno 1 - 10
of 53
pro vyhledávání: '"Jeffrey W. Sleight"'
Autor:
Will Shanks, Jay M. Gambetta, Jeffrey W. Sleight, Matthias Steffen, Douglas McClure, Oliver Dial, Y.-K.-K. Fung, Conal E. Murray
Superconducting qubits are sensitive to a variety of loss mechanisms including dielectric loss from interfaces. By changing the physical footprint of the qubit it is possible to modulate sensitivity to surface loss. Here we show a systematic study of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::28ec9f460e83dde8b4068442b2260f8b
Publikováno v:
Microscopy and Microanalysis. 17:889-895
The ability to prepare multiple cross-section transmission electron microscope (XTEM) samples from one XTEM sample of specific sub-10 nm features was demonstrated. Sub-10 nm diameter Si nanowire (NW) devices were initially cross-sectioned using a dua
Autor:
Paul M. Solomon, Wilfried Haensch, Steve Laux, Shawn G. Thomas, Jim Cai, Leland Chang, Jeffrey W. Sleight, Pierre Tomasini, S.J. Koester, Siyu Koswatta, Isaac Lauer, Stephen W. Bedell, Amlan Majumdar
Publikováno v:
ECS Transactions. 33:357-361
Introduction. The ability to scale CMOS to future technology nodes is jeopardized primarily by power constraints. Supply voltage scaling is the best method to reduce power consumption in logic circuits; however, the thermionic nature of the turn-off
Autor:
Hasan M. Nayfeh, Nivo Rovedo, Andres Bryant, Shreesh Narasimha, Arvind Kumar, Xiaojun Yu, Ning Su, Jeffrey W. Sleight, Robert R. Robison, Werner Rausch, Hari Mallela, Greg Freeman
Publikováno v:
IEEE Transactions on Electron Devices. 56:3097-3105
Lateral asymmetric channel doping is applied to 45-nm technology NFET devices. The measured effective drain-current enhancement over coprocessed symmetric control devices is 10%. Analysis reveals that the dominant physical mechanism, which accounts f
Autor:
M. Guillorn, Jeffrey W. Sleight, Jemima Gonsalves, Christian Lavoie, Sebastian Engelmann, Siyuranga O. Koswatta, Fei Liu, Zhen Zhang, J. Newbury, Ashish Baraskar, Paul M. Solomon, A. Pyzyna, Yu Zhu, Wei Song, Cyril Cabral, S. W. Bedell, Michael F. Lofaro, Marinus Hopstaken, Li Yang, Mark Raymond, Kenneth P. Rodbell, Ahmet S. Ozcan, C. Witt
Publikováno v:
IEEE Electron Device Letters. 34:723-725
Contact resistances are directly measured for contacts with sizes from 25 to 330 nm using e-beam based nano-TLM devices. Record low contact resistivities ~1.5 × 10-9 Ω· cm2 are extracted from Ni(Pt) silicide contacts on in situ boron-doped Si0.7Ge
Autor:
Sebastian Engelmann, Karthik Balakrishnan, C. M. Breslin, Guy M. Cohen, Isaac Lauer, Szu-Lin Cheng, Sarunya Bangsaruntip, Lynne Gignac, J. Newbury, Josephine B. Chang, Robert L. Bruce, Markus Brink, Jeffrey W. Sleight, D. Klaus, Amlan Majumdar, M. Guillorn, A. Pyzyna
Publikováno v:
2013 IEEE International Electron Devices Meeting.
We present results from gate-all-around (GAA) silicon nanowire (SiNW) MOSFETs fabricated using a process flow capable of achieving a nanowire pitch of 30 nm and a scaled gate pitch of 60 nm. We demonstrate for the first time that GAA SiNW devices can
Autor:
L.A. Bair, R. Flatley, D.A. Antoniadis, G.J. Grula, K.R. Mistry, Jeffrey W. Sleight, B. Miner
Publikováno v:
IEEE Transactions on Electron Devices. 46:2201-2209
An in-depth analysis of the role of parasitic bipolar gain reduction in 0.25-/spl mu/m partially depleted SOI MOSFETs is presented, considering both dc characteristics as well as circuit operation. The effect of channel doping, silicide proximity, an
Autor:
Amlan Majumdar, R. Venigalla, Steven J. Koester, D. Dobuzinsky, Jeffrey W. Sleight, Judson R. Holt, Zhibin Ren, W. Haensch
Publikováno v:
IEEE Electron Device Letters. 29:515-517
We have fabricated undoped-body short-channel extremely thin silicon-on-insulator (ETSOI) field-effect transistors (FETs) with 8-nm SOI thickness that exhibit the expected short-channel benefit compared with doped partially depleted SOI (PDSOI) FETs.
Publikováno v:
IEEE Electron Device Letters. 27:588-590
Off-state modulation of the floating-body potential in partially depleted silicon-on-insulator (PDSOI) transistors from the 90-nm technology generation is observed using pulsed current-voltage (I-V) measurements. Varying the off-value of the gate vol
Autor:
Mukesh Khare, James N. Pan, D.V. Singh, Kathryn W. Guarini, Hasan M. Nayfeh, John M. Hergenrother, B.L. Tessier, John A. Ott, Meikei Ieong, Linda Black, O. Dokumaci, Wilfried Haensch, R. Venigalla, Zhibin Ren, Jeffrey W. Sleight, Wesley C. Natzle, Dureseti Chidambarrao
Publikováno v:
IEEE Electron Device Letters. 27:288-290
In this letter, the effect of longitudinal uniaxial mechanical stress on electron mobility in high-performance fully depleted ultrathin silicon-on-insulator nFETs with a raised source/drain (RSD) architecture and channel lengths ranging from 1 /spl m