Zobrazeno 1 - 10
of 19
pro vyhledávání: '"Jeffrey A. Stuecheli"'
Publikováno v:
IEEE Micro. 41:7-14
The IBM POWER10 processor represents the 10th generation of the POWER family of enterprise computing engines. It is built on a balance of computation and bandwidth, delivered by powerful processing cores and intrachip interconnect, respectively. Mult
Autor:
Pradip Bose, William J. Starke, Christian Zoellin, Ramon Bertran, Satish Kumar Sadasivam, Alper Buyuktosunoglu, Silvia M. Müller, Matthias Pflanz, Robert K. Montoye, Michael Normand Goulet, John-David Wellman, Nagu Dhanwada, Dung Q. Nguyen, Marcy E. Byers, José E. Moreira, Balaram Sinharoy, Richard J. Eickemeyer, Christopher Gonzalez, Thompto Brian W, Andreas Wagner, Karthik Swaminathan, Hans M. Jacobson, Nandhini Chandramoorthy, Michael Stephen Floyd, Jeffrey A. Stuecheli, Rahul M. Rao
Publikováno v:
ISCA
We present the novel micro-architectural features, supported by an innovative and novel pre-silicon methodology in the design of POWER10. The resulting projected energy efficiency boost over POWER9 is 2.6x at core level (for SPECint) and up to 3x at
Autor:
Elaine R. Palmer, Kenneth Alan Goldman, Bharata Bhasker Rao, Hani Jamjoom, Lawrence Roy, Janani Janakirman, Brad Frey, Laurent Dufour, Ramachandra N. Pai, John M. Ludden, Cathy May, Guerney D. H. Hunt, Jeffrey A. Stuecheli, Wendel Glenn Voigt, Enriquillo Valdez, Sukadev Bhattiprolu, Mohit Kapur, Rick Boivie, William A. Starke, Paul Mackerras, Michael V. Le, Ryan P. Grimm
Publikováno v:
EuroSys
This paper presents Protected Execution Facility (PEF), a virtual machine-based Trusted Execution Environment (TEE) for confidential computing on Power ISA. PEF enables protected secure virtual machines (SVMs). Like other TEEs, PEF verifies the SVM p
Publikováno v:
Hot Chips Symposium
Autor:
Fabio Checconi, John A. Gunnels, Jeffrey A. Stuecheli, Fabrizio Petrini, Xing Liu, Jee Choi, Daniele Buono, Xinyu Que
Publikováno v:
IPDPS
In this paper we evaluate the performance of a large-scale POWER8 symmetric multiprocessor (SMP) system with eight processors. We focus our attention on cache and memory subsystems, analyzing the characteristics that have a direct impact on high-perf
Publikováno v:
IEEE Micro. 31:90-98
To alleviate bottlenecks in this era of many-core architectures, the authors propose a virtual write queue to expand the memory controller's scheduling window through visibility of cache behavior. Awareness of the physical main memory layout and a fo
Autor:
James A. Marcella, Jeffrey A. Stuecheli, Brad W. Michael, Stephen J. Powell, John Steven Dodson, William J. Starke, Eric E. Retter
Publikováno v:
IBM Journal of Research and Development. 62:3:1-3:13
The IBM POWER9 processor chipset provides a variety of system memory architecture interfaces to enable highly differentiated system offerings: a high bandwidth, high capacity, highly reliable, buffered architecture; a compute-density-optimized direct
Autor:
C. Wollbrink, L. B. Arimilli, B. Allison, Bartholomew Blaner, Jeffrey A. Stuecheli, William J. Starke, J. D. Irish, Daniel M. Dreps
Publikováno v:
IBM Journal of Research and Development. 62:8:1-8:8
Open Coherent Accelerator Processor Interface (OpenCAPI) is a new industry-standard device interface that enables the development of host-agnostic devices that can coherently connect to any host platform that supports the OpenCAPI standard. This in t
Autor:
T. W. Pouarz, J. Abdulhafiz, K. D. Thompson, L. A. McConville, B. S. Nelson, F. D. Lewis, John M. Ludden, Bruce Wile, P. E. Milling, Bing-Lun Chu, G. M. Heiling, R. D. Peterson, Jason R. Baumgartner, Michael L. Behm, J. H. Klaus, Jeffrey A. Stuecheli, Viresh Paruthi, A. D. Romonosky, Jackson Jonathan, W. E. Bucy, T. Le, Wolfgang Roesner, D. J. Klema, J. R. Reysa, D. W. Victor
Publikováno v:
IBM Journal of Research and Development. 46:53-76
This paper describes the methods and simulation techniques used to verify the microarchitecture design and functional performance of the IBM POWER4 processor and the POWER4-based Regatta system. The approach was hierarchical, based on but considerabl
Publikováno v:
PACT
To achieve high efficiency and prevent destructive interference among multiple divergent workloads, the last-level cache of Chip Multiprocessors has to be carefully managed. Previously proposed cache management schemes suffer from inefficient cache c