Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Jeffery B. Maxson"'
Autor:
Trejo Rust, David McCarthy, Min Dai, Michael Brodfuehrer, Lingjie Wang, Colleen Meagher, Bruce Dyer, Raymond Van Roijen, Michael D. Steigerwalt, Javier Ayala, Gasner Barthold, Jeffery B. Maxson, Randal Bakken
Publikováno v:
2017 28th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
A small but persistent signal in wafer slot order was observed at functional test, affecting logic yield. Through wafer slot Randomization at several operations in the route a process step within high-k metal gate formation was suspected to be causin
Publikováno v:
Chemistry of Materials. 6:2222-2226
We report electrochemical and in situ atomic force microscopy observations of the formation of a new class of crystalline organic monolayer, which consists of a conductive organic salt containing bis(ethylenedithiolo)-tetrathiafulvalene (ET), on high
Autor:
Javier Ayala, W. Steer, S. Conti, K. Tabakman, Richard O. Henry, Chienfan Yu, E. Meyette, R. Arndt, J. Levy, R. Burda, R. Keyser, R. Van Roijen, Jeffery B. Maxson
Publikováno v:
2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.
In semiconductor manufacturing, we expect the cause of defects to be process or tool related. However, at the 90 nm technology node and beyond we find that defects can be caused by issues related to the wafers' environment, such as processing of othe
Autor:
Steven C. Catlett, R. Logan, Javier Ayala, R. Van Roijen, R. Ramachandran, Joseph F. Shepard, Jeffery B. Maxson, S. Ruegsegger, B. Rawlins, C. Collins, Kevin K. Dezfulian, K. Barker, T. Rust, R. Singh, H. Boiselle
Publikováno v:
2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
The complexity of modern manufacturing processes has sharply increased the number of steps affecting device and circuit performance. We discuss a number of critical steps, their control methodology and how to minimize the time to detect. Product test
Autor:
F. Scholl, Daewon Yang, Huilong Zhu, Effendi Leobandung, J. Colt, D. Chen, D. Leach, Jeffery B. Maxson, Mahender Kumar
Publikováno v:
2007 IEEE Symposium on VLSI Technology.
This paper presents a simple, effective, and economical method to improve the yield of high performance 65 nm SOI CMOS technology using dual stress nitride liner (DSL) for performance enhancement. Sputtering is used to reduce the complexity caused by