Výsledky vyhledávání - "Jean-FrancOis damlencourt"

Source and Drain Contact Module for FDSOI MOSFETs : Silicidation and Strain Engineering

Autor: Sophie Bernasconi, David Cooper, Jean-Francois Damlencourt, Yves Morand, Fabrice Nemouchi, Sylvie Favier, Jean-Michel Hartmann, Veronique Carron

Publikováno v: ECS Transactions. 58:239-248

Strained SiGe and SiC sources and drains are planned to be used in sub-28nm FDSOI devices in order to improve the carriers mobility. Consequently, silicide-induced relaxation of strained epitaxial layers is a key issue to address in order to fully be

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c04414bbd663a5945ccb202753ab900d
https://doi.org/10.1149/05809.0239ecst

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Evaluation Of Ni(Si1-xGex) and Pt(Si1-xGex) Contact Resistance for FD-SOI PMOS Metallic Source and Drain

Autor: Fabienne Allain, Fabrice Nemouchi, V. Carron, Maud Vinet, Yves Morand, Jean-Francois Damlencourt, D. Lafond, Emilie Bourjot, Sophie Bernasconi, Olga Cueto

Publikováno v: ECS Transactions. 50:197-204

To improve 20nm FD-SOI pMOS transistor performances, salicide process must be optimized on SiGe source&drain. In this paper, we propose an investigation on Ni and Pt/Si1-xGex (x=0.15, 0.3) systems. In a first part, process window is studied to determ

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::733f4d41b81c8bbd34503cd8c4f16f12
https://doi.org/10.1149/05009.0197ecst

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Dual strained channel CMOS in FDSOI architecture: New insights on the device performance

Publikováno v: Solid-State Electronics. :9-15

We report an original Dual Strained Channel On Insulator (DSCOI) Fully Depleted CMOS architecture by co-integrating nFETs on sSOI and pFETs on Si/c-SiGe/(s)SOI with a TiN/HfO 2 gate stack (EOT = 1.15 nm) and down to 40 nm gate lengths. We demonstrate

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b1a86fd3778e2c0a7f0956957e6f25b3
https://doi.org/10.1016/j.sse.2011.06.024

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Transport Properties of 3D Vertically Stacked SiGe and SiGeC Nanowires

Autor: Irina Ionica, Emeline Saracco, Sorin Cristoloveanu, Caroline Bonafos, Jean-Francois Damlencourt, A. Diab

Publikováno v: ECS Transactions. 35:157-162

One of the trends in microelectronics is to explore nanowire gate-all-around structures and alternative channel materials with interesting electrical transport properties. We present the electrical transport in three-dimensional vertically stacked ge

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8bf78717c6daabac5080014d7a340b36
https://doi.org/10.1149/1.3570791

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Low Temperature Epitaxy of Si and SiGe Using Disilane Based Chemistry for Electronic Purposes

Autor: Jean-Francois Damlencourt

Publikováno v: ECS Transactions. 28:343-348

For future CMOS technologies, epilayers such as Si, SiGe and SiC are intensively investigated as candidates for Sources and Drains and channel materials. A low thermal budget and high growth rate is mandatory, mainly for FDSOI applications in order t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3c76418f0be521103ae293a2e3ca1185
https://doi.org/10.1149/1.3375620

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3D Suspended Nanowires Integration for CMOS and Beyond

Autor: Emeline Saracco, K. Tachi, V. Maffini-Alvaro, Cecilia Dupre, Jean-Francois Damlencourt, Thomas Ernst, Jean-Michel Hartmann, Nathalie Vulliet, Stéphane Bécu, Alexandre Hubert, Caroline Bonafos, C. Vizioz, E. Bernard, Peter Cherns, Jean-Philippe Colonna

Publikováno v: ECS Transactions. 25:471-478

Novel 3D stacked Gate-All-Around (GAA) nanowires CMOS architectures were developed recently for their very low leakage potentialities and high current drivability for sub-22nm nodes. In this paper, we will discuss some challenges and innovations asso

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b66544f5194908aee5db362da09beb74
https://doi.org/10.1149/1.3203985

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Fabrication of Suspended Ge-rich Nanowires by Ge Enrichment Technique for Multi-channel Devices

Autor: Caroline Bonafos, C. Vizioz, Pierette Rivallin, Yves Morand, Pauline Gautier, Pier Fransesco Fazzini, Dominique Lafond, Jean-Michel Hartmann, Véronique Benevent, Sophie Bernasconi, Jean-Francois Damlencourt, Emeline Saracco, Thomas Ernst

Publikováno v: ECS Transactions. 19:207-212

This paper presents a new top-down method to fabricate Ge-rich nanowires for multi-channel devices by Ge enrichment technology. 3 dimensional Ge nanowire stacks have been fabricated and characterized by SEM, TEM, EDX. Nanowires obtained are single cr

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a063c96981c789f9c8806543a8d7e14d
https://doi.org/10.1149/1.3118946

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Low-Temperature Measurements on Germanium-on-Insulator pMOSFETs: Evaluation of the Background Doping Level and Modeling of the Threshold Voltage Temperature Dependence

Autor: Bruno Ghyselen, Sorin Cristoloveanu, Cyrille Le Royer, Laurent Clavelier, Eric Guiot, Krunoslav Romanjek, William Van Den Daele, Jean-Francois Damlencourt, Emmanuel Augendre

Publikováno v: ECS Transactions. 19:145-152

Fully depleted GeOI (Germanium on Insulator) pMOSFETs with HfO2/TiN gate stack and Si-passivation are studied at low temperature. The impact of the starting Ge material and N-type channel doping on threshold voltage is examined. As there is no eviden

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b3c1290fd6e8ea19aab88f2812fe365a
https://doi.org/10.1149/1.3117403

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