Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Jean Audet"'
Autor:
Yanyan Zhang, Pavel Roy Paladhi, Sungjun Chun, Lei Shan, Jose A. Hejase, Jean Audet, Mahesh Bohra, Wiren D. Becker, Daniel M. Dreps
Publikováno v:
2019 IEEE 28th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
A novel edge card connector design approach with tunable signal integrity (SI) properties is proposed. The tunability is achieved through the presence or absence of a grounded conductive fixture in between the connector pin rows. The main purpose of
Autor:
Brian Samuel Beaman, Jean Audet
Publikováno v:
International Symposium on Microelectronics. 2017:000659-000662
Land grid array (LGA) sockets are commonly used for industry standard and custom microprocessors to meet the increased performance challenges for a variety of server applications. Along with the need for increased high speed signaling capabilities co
Autor:
Kwang Won Choi, Keiichi Hirabayashi, Edmund Blackshear, Jean Audet, David B. Stone, Eric W. Tremble
Publikováno v:
2019 IEEE 69th Electronic Components and Technology Conference (ECTC).
High speed SerDes standards demand higher speed signals for the next generation - 112Gbit/sec. The integrity of signals is affected strongly by the physical characteristics of the printed circuit substrate in a 112Gbit/s high speed device. The effect
Publikováno v:
2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
This paper examines methods to electromagnetically model a hybrid land grid array (HLGA) connector and its associated printed circuit board (PCB) via individually with the goal of achieving the best correlation between their cascade and when modelled
Autor:
Emmanuel Tetsi, Gilles Philippot, BORD MAJEK Isabelle, Cyril Aymonier, Jean Audet, Roxan Lemire, Laurent Bechou, Dominique Drouin
Publikováno v:
44th International Conference on Micro and Nanoengineering (MNE 2018)
44th International Conference on Micro and Nanoengineering (MNE 2018), Sep 2018, Copenhague, Denmark
HAL
44th International Conference on Micro and Nanoengineering (MNE 2018), Sep 2018, Copenhague, Denmark
HAL
International audience
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::b2c00b467342327bb392206bead5b19d
https://hal.archives-ouvertes.fr/hal-01957047
https://hal.archives-ouvertes.fr/hal-01957047
Autor:
Jean Audet, Dominique Drouin, Laurent Bechou, Emmanuel Tetsi, Isabelle Bord Majek, Cyril Aymonier, Roxan Lemire, Gilles Philippot
Publikováno v:
2018 IEEE 68th Electronic Components and Technology Conference (ECTC)
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), May 2018, San Diego, United States. ⟨10.1109/ECTC.2018.00212⟩
2018 IEEE 68th Electronic Components and Technology Conference (ECTC), May 2018, San Diego, United States. ⟨10.1109/ECTC.2018.00212⟩
The integration of decoupling capacitors with high capacitance density on interposers for 3D electronics packaging requires innovative approaches for dielectric layer deposition. In this paper, we report the development of a novel and low-cost spray
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2cd5346c86360431ec5ef766b6070f4f
https://hal.archives-ouvertes.fr/hal-01885255
https://hal.archives-ouvertes.fr/hal-01885255
Autor:
Wiren D. Becker, Young H. Kwark, Matthew Richardson, Jose A. Hejase, Christian W. Baks, Daniel M. Dreps, Junyan Tang, Jean Audet
Publikováno v:
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
This paper studies integration aspects of DC blocking capacitors in differential high speed bus channels. The presence of a DC blocking capacitor in the signal path can present an impedance mismatched medium which can lead to signal degradation. Inte
Autor:
Glen A. Wiedemeier, Lloyd A. Walls, Jose A. Hejase, Francesco Preda, Jean Audet, Daniel Douriet, Dale Becker, Junyan Tang, Sungjun Chun, Megan Nguyen, Daniel M. Dreps
Publikováno v:
2017 IEEE 67th Electronic Components and Technology Conference (ECTC).
A 19.2 Gb/s per lane link with IBM's latest POWER8 processor module has been analyzed. This paper presents the overview of the high-speed link design from the signal integrity point of view. Design approaches in package and printed circuit board (PCB
Autor:
Emmanuel Tetsi, Roxan Lemire, Isabelle Bord Majek, Dominique Drouin, Laurent Bechou, Jean Audet, Gilles Philippot, Cyril Aymonier
Publikováno v:
physica status solidi (a)
physica status solidi (a), Wiley, 2018, 215 (23), 1800478 (11 p.). ⟨10.1002/pssa.201800478⟩
physica status solidi (a), Wiley, 2018, 215 (23), 1800478 (11 p.). ⟨10.1002/pssa.201800478⟩
International audience; Metal‐insulator‐metal (MIM) capacitors with Ba0.6Sr0.4TiO3 (BST) thin films as insulating layers are fabricated using a novel, fast, and low‐cost method. On one hand, the process lies in the swift, continuous, and scalab
Autor:
Hsichang Liu, Scott Alan Moore, Masahiro Fukui, Kenji Terada, Brian R. Sundlof, Masaaki Harazono, Tomoyuki Yamada, Teruya Fujisaki, Hongqing Zhang, Sushumna Iruvanti, Jean Audet, Charles L. Reynolds, Yi Pan
Publikováno v:
International Symposium on Microelectronics. 2013:000538-000545
This paper describes a Chip Scale Package (CSP) development project and evaluation of the corresponding organic laminate material. Chip scale packaging can combine the strengths of various packaging technologies, such as the large size and performanc