Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Jayen J. Desai"'
Autor:
Nevine Nassif, Jason Crop, Brian Brock, Christopher J. Bostak, Jayen J. Desai, Dave Bradley, Arvind Raghavan, C. Houghton, Daniel W. Krueger, Olivier Franza, C. Morganti, Bill Bowhill, Sal Bhimji, B. Stackhouse, Mendoza Oscar, Zibing Yang, Matthew Becker
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:92-104
The next generation enterprise Xeon server processor maximum configuration supports 18 dual-threaded 64 bit Haswell cores, 45 MB L3 cache, 4 DDR4–2133 MHz memory channels, 40 8 GT/s PCIe lanes, and 40 9.6 GT/s QPI lanes. The processor has 5.56 B tr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e24b3135ebe4be2d20a49543de8b8287
https://doi.org/10.1109/jssc.2015.2472598
https://doi.org/10.1109/jssc.2015.2472598
Autor:
P. Gronowski, B. Cherkauer, Daniel W. Krueger, B. Stackhouse, C. Morganti, M.K. Gowan, Dave Bradley, E. Francom, S. Troyer, Christopher J. Bostak, Jayen J. Desai, Sal Bhimji
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:18-31
This paper describes an Itanium processor implemented in 65 nm process with 8 layers of Cu interconnect. The 21.5 mm by 32.5 mm die has 2.05B transistors. The processor has four dual-threaded cores, 30 MB of cache, and a system interface that operate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e462ba22f3dd3e25996f2e4277d45c7
https://doi.org/10.1109/jssc.2008.2007150
https://doi.org/10.1109/jssc.2008.2007150
Autor:
Arvind Raghavan, Dave Bradley, Zibing Yang, C. Houghton, Matthew Becker, B. Stackhouse, Daniel W. Krueger, Olivier Franza, Bill Bowhill, Sal Bhimji, Nevine Nassif, C. Morganti, Christopher J. Bostak, Jason Crop, Jayen J. Desai
Publikováno v:
ISSCC
The next-generation enterprise Xeon server processor maximum configuration supports 18 dual-threaded 64b Haswell cores [1], 45MB L3 cache, 4 DDR4-2133MHz memory channels, 40 8GT/s PCIe lanes, and 60 9.6GT/S QPI lanes. The processor has 5.56B transist
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6b50772a373a14368c865919a2c7896d
https://doi.org/10.1109/isscc.2015.7062934
https://doi.org/10.1109/isscc.2015.7062934
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:218-228
An Itanium Architecture microprocessor in 90-nm CMOS with 1.7B transistors implements a dynamically-variable-frequency clock system. Variable frequency clocks support a power management scheme which maximizes processor performance within a configured
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99fa1905197bd364db17a2fae58a0138
https://doi.org/10.1109/jssc.2005.859879
https://doi.org/10.1109/jssc.2005.859879
Autor:
Jayen J. Desai, Elad Alon, S. Naffziger, T. Grutkowski, B. Stackhouse, Mark Horowitz, D. Josephson
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:197-209
The design of the high end server processor code named Montecito incorporated several ambitious goals requiring innovation. The most obvious being the incorporation of two legacy cores on-die and at the same time reducing power by 23%. This is an eff
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7da7ee8301e9a65bb0290b2ae693f94
https://doi.org/10.1109/jssc.2005.859894
https://doi.org/10.1109/jssc.2005.859894