Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Jaroslav Pjencak"'
Publikováno v:
2022 14th International Conference on Advanced Semiconductor Devices and Microsystems (ASDAM).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a9ec1167617060c83e870e7247dfc79f
https://doi.org/10.1109/asdam55965.2022.9966755
https://doi.org/10.1109/asdam55965.2022.9966755
Publikováno v:
Advances in Electrical and Electronic Engineering, Vol 3, Iss 2, Pp 265-268 (2004)
High quality silicon epitaxial layers are inevitable in bipolar and/or unipolar technology. However, its properties are not as easy characterized as those of bulk material. The recombination lifetime is dominated by surface/interface recombination fo
Externí odkaz:
https://doaj.org/article/358d28fe8862451bac6f68c3af4fdde7
Autor:
Johan Janssens, Weize Chen, Rick Jerome, Jaroslav Pjencak, Mark Griswold, Santosh Menon, Moshe Agam
Publikováno v:
2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD).
A cost effective method to extend a 70V bulk BCD technology to a 200V SOI BCD technology is presented. The new approach replaces the floating n-type buried layer (NBL) in the bulk technology with the buried oxide (BOX) in silicon-on-insulator (SOI).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dadb415eed05b6a0406035ea438367fc
https://doi.org/10.23919/ispsd50666.2021.9452294
https://doi.org/10.23919/ispsd50666.2021.9452294
Publikováno v:
2021 33rd International Symposium on Power Semiconductor Devices and ICs (ISPSD).
The isolation capabilities of the Floating N-type Buried Layer (NBL) architecture are discussed and explained in reference to connected NBL. The non-deterministic NBL potential requires new considerations for lateral and vertical parasitics. These pa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e53ec30d51b9bd5bd55cab5b2f86198
https://doi.org/10.23919/ispsd50666.2021.9452202
https://doi.org/10.23919/ispsd50666.2021.9452202
Physical and Electrical Characterization of Deep Trench Isolation in Bulk Silicon and SOI Substrates
Autor:
Sallie Hose, Lahcen Boukhanfra, Lan Su, Masaichi Eda, Rick Jerome, Weize Chen, Jaroslav Pjencak, Thomas F. Long, Johan Janssens, Moshe Agam, Kenn Bates
Publikováno v:
2021 32nd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
In this paper the authors present case studies for physical and electrical characterization of Deep Trench Isolation (DTI) in bulk silicon and SOI substrates. For bulk silicon, experimental results demonstrate how the effectiveness of the isolation i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ee709b0dc0ae9329ba2354d27b3c85ae
https://doi.org/10.1109/asmc51741.2021.9435655
https://doi.org/10.1109/asmc51741.2021.9435655
Publikováno v:
2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD).
In a given multipurpose BCD technology, the device implants are set by the main workhorse devices. Typically, doping levels are determined by optimizing Rsp and other key properties of the main devices, often settling with optimized Rsp-Bvdss trade-o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::817e51b1ce429e0d0c238624bba16fce
https://doi.org/10.1109/ispsd46842.2020.9170036
https://doi.org/10.1109/ispsd46842.2020.9170036
Publikováno v:
2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD).
Novel design approach for LDMOS device operating at voltages exceeding 100V is demonstrated and architecture to address all aspects of critical electric field is described. As a bonus, no changes in doping conditions required to achieve the device ta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f006fad7b5fc85674c42bd792922a198
https://doi.org/10.1109/ispsd.2018.8393664
https://doi.org/10.1109/ispsd.2018.8393664
Autor:
Thierry Coffi Herve Yao, Moshe Agam, Ladislav Seliga, Jaroslav Pjencak, Agajan Suwhanov, Dusan Prejda
Publikováno v:
ESSDERC
Integration of isolated LDMOS transistors in smart power process is subjected to bipolar parasitics due to multi layers constructions that are needed for high voltage operation. These parasitics need to be minimized to assure proper circuit functiona
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26e665ff386ecb4bef2a642d4b8573c1
https://doi.org/10.1109/essderc.2016.7599646
https://doi.org/10.1109/essderc.2016.7599646
Publikováno v:
2016 ELEKTRO.
This paper reports design and optimization of low capacitance, dual direction ESD device for new generation of IPD (Integrated Passive Devices) technology by use of TCAD simulator. Two types of ESD protection (B2B diode and Dual SCR) have been design
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20818d64d9e7889eed93dbe9476dc330
https://doi.org/10.1109/elektro.2016.7512101
https://doi.org/10.1109/elektro.2016.7512101
Publikováno v:
The Tenth International Conference on Advanced Semiconductor Devices and Microsystems.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76966d7f2ea8a1520a2c2d785058cab1
https://doi.org/10.1109/asdam.2014.6998698
https://doi.org/10.1109/asdam.2014.6998698