Zobrazeno 1 - 10
of 34
pro vyhledávání: '"Janko Versluijs"'
Autor:
Yannick Hermans, Chen Wu, Nunzio Buccheri, Filip Schleicher, Janko Versluijs, Daniel Montero, Bappaditya Dey, Patrick Wong, Paulina Rincon-Delgadillo, Seongho Park, Zsolt Tokei, Philippe Leray, Sandip Halder
Publikováno v:
Optical and EUV Nanolithography XXXVI.
Autor:
Basoene Briggs, Zaid El-Mekki, Jürgen Bömmels, Kurt G. Ronse, Stephane Lariviere, Peter De Bisschop, Dan Mocuta, Bogumila Kutrzeba Kotowska, Dieter Van den Heuvel, Joost Bekaert, Danny Wan, Greg McIntyre, Arindam Mallik, Nicolas Jourdan, Ivan Ciofi, Marleen H. van der Veen, Janko Versluijs, Patrick Verdonck, Ming Mao, Christopher J. Wilson, Els Kesters, Stefan Decoster, Victor Blanco, Zsolt Tőkei, Nancy Heylen, Christophe Beral, Eric Hendrickx, Ryoung-han Kim
Publikováno v:
Extreme Ultraviolet (EUV) Lithography IX.
The semiconductor scaling roadmap shows the continuous node to node scaling to push Moore’s law down to the next generations. In that context, the foundry N5 node requires 32nm metal pitch interconnects for the advanced logic Back- End of Line (BEo
Autor:
Janko Versluijs, Stefan Decoster, Arindam Mallik, Sandip Halder, Frederic Lazzarino, W. Li, Gayle Murdoch, L. Petersen Barbosa Lima
Publikováno v:
Advanced Etch Technology for Nanopatterning VII.
While the semiconductor industry is almost ready for high-volume manufacturing of the 7 nm technology node, research centers are defining and troubleshooting the patterning options for the 5 nm technology node (N5) and below. The target dimension for
Autor:
Arindam Mallik, Basoene Briggs, Janko Versluijs, Christopher J. Wilson, Juergen Bommels, Job Soethoudt, Zsolt Tokei
Publikováno v:
2018 China Semiconductor Technology International Conference (CSTIC).
CMOS area scaling to N5 dimensions will have interconnect metal pitch around 30nm. Patterning such small features, using 193 ArF immersion lithography (193i), is only possible with pitch multiplication techniques such as SADP, SAQP, SAOP, etc. An add
Autor:
Carlos Fonseca, Janko Versluijs, Marc Demand, Serge Biesemans, Satoru Shimura, Monique Ercken, Philippe Foubert, Shinji Kobayashi, Miyazaki Shinobu, Kathleen Nafus, Soichiro Okada
Publikováno v:
SPIE Proceedings.
We discuss edge placement errors (EPE) for multi-patterning of Mx critical layers using ArF lithography. Specific focus is placed on the block formation part of the process. While plenty of literature characterization data exist on spacer formation,
Autor:
Eddy Kunnen, Steven Demuynck, Julien Ryckaert, Janko Versluijs, Juergen Boemmels, Mohand Brouri
Publikováno v:
SPIE Proceedings.
It is clear today that further scaling towards smaller dimensions and pitches requires a multitude of additional process steps. Within this work we look for solutions to achieve a middle of line 193i based patterning scheme for N7 logic at a contacte
Autor:
Janko Versluijs, Geert Van den bosch, Pieter Blomme, Jan Van Houdt, Chi Lim Tan, Laurent Souriau
Publikováno v:
2014 IEEE 6th International Memory Workshop (IMW).
Fully planar NAND Flash arrays operate with very low coupling ratio (CR), and the CR reduces even further when scaling below 20 nm half-pitch. As a consequence, they suffer from programming saturation due to excessive leakage through the intergate di
Publikováno v:
SPIE Proceedings.
Spacer based SADP (Self-Aligned Double Patterning) is used increasingly in IC manufacturing as design rules outstrip the resolution capabilities of traditional single exposure lithography processes. In this paper, a 15nm half pitch SADP process based
Autor:
David Hellin, Isabelle Orain, Chi Lim Tan, Werner Boullart, Patrick Wong, Janko Versluijs, Diziana Vangoidsenhoven, X. P. Shi, B. Coenegrachts, Nadia Vandenbroeck, Laurent Souriau, Vincent Wiaux, Harold Dekkers, Justin Albert, Yoshie Kimura, K. Xu, Johan Vertommen
Publikováno v:
SPIE Proceedings.
This paper discusses the approach for patterning 15nm Half Pitch (HP) structures using EUV lithography combined with Self-Aligned Double Patterning (SADP). A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim,
Autor:
Janko Versluijs, Vincent Truffert, Gayle Murdoch, Vincent Wiaux, Monique Ercken, Steven Demuynck, Darko Trivkovic, Laurent Souriau, Peter De Bisschop, Eddy Kunnen
Publikováno v:
SPIE Proceedings.
The demand for ever shrinking semiconductor devices is driving efforts to reduce pattern dimensions in semiconductor lithography. In this work, the aim is to find a single patterning litho solution for a 28nm technology node using 193nm immersion lit