Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Jani Makipaa"'
Autor:
Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Jani Mäkipää, Arto Rantala, Matti Sopanen, Mikko Kaltiokallio
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 5, Iss 2, Pp 57-68 (2015)
To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all appli
Externí odkaz:
https://doaj.org/article/c1af18f6b459465a89636a8763954d5c
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 2, Iss 2, Pp 180-196 (2012)
This paper presents the first known timing-error detection (TED) microprocessor able to operate in subthreshold. Since the minimum energy point (MEP) of static CMOS logic is in subthreshold, there is a strong motivation to design ultra-low-power syst
Externí odkaz:
https://doaj.org/article/5877aadf27d146b68c44d6d8ae475441
Publikováno v:
Journal of Low Power Electronics and Applications, Vol 6, Iss 3, p 17 (2016)
The importance of energy-constrained processors continues to grow especially for ultra-portable sensor-based platforms for the Internet-of-Things (IoT). Processors for these IoT applications primarily operate at near-threshold (NT) voltages and have
Externí odkaz:
https://doaj.org/article/dd03482df97c434fada283f11d36b467
Publikováno v:
Koskinen, L, Hiienkari, M, Mäkipää, J & Turnquist, M J 2016, ' Implementing minimum-energy-point systems with adaptive logic ', IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 4, 7160774, pp. 1247-1256 . https://doi.org/10.1109/TVLSI.2015.2442614
Timing-error-detection (TED)-based systems have been shown to reduce power consumption or increase yield due to reduced margins. This paper shows that the increased adaptability can be a great advantage in the system design in addition to the well-kn
Publikováno v:
Journal of Low Power Electronics and Applications; Volume 6; Issue 3; Pages: 17
Turnquist, M, Hiienkari, M, Mäkipää, J & Koskinen, L 2016, ' A fully integrated 2:1 self-oscillating switched-capacitor DC-DC converter in 28 nm UTBB FD-SOI ', Journal of Low Power Electronics and Applications, vol. 6, no. 3, 17 . https://doi.org/10.3390/jlpea6030017
Journal of Low Power Electronics and Applications, Vol 6, Iss 3, p 17 (2016)
Turnquist, M, Hiienkari, M, Mäkipää, J & Koskinen, L 2016, ' A fully integrated 2:1 self-oscillating switched-capacitor DC-DC converter in 28 nm UTBB FD-SOI ', Journal of Low Power Electronics and Applications, vol. 6, no. 3, 17 . https://doi.org/10.3390/jlpea6030017
Journal of Low Power Electronics and Applications, Vol 6, Iss 3, p 17 (2016)
The importance of energy-constrained processors continues to grow especially for ultra-portable sensor-based platforms for the Internet-of-Things (IoT). Processors for these IoT applications primarily operate at near-threshold (NT) voltages and have
Autor:
Matti Sopanen, Arto Rantala, Jani Makipaa, Markus Hiienkari, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Mikko Kaltiokallio
Publikováno v:
Journal of Low Power Electronics and Applications
Volume 5
Issue 2
Pages 57-68
Journal of Low Power Electronics and Applications, Vol 5, Iss 2, Pp 57-68 (2015)
Hiiekari, M, Teittinen, J, Koskinen, L, Turnquist, M J, Mäkipää, J, Rantala, A, Sopanen, M & Kaltiokallio, M 2015, ' A robust ultra-low voltage CPU utilizing timing-error prevention ', Journal of Low Power Electronics and Applications, vol. 5, no. 2, pp. 57-68 . https://doi.org/10.3390/jlpea5020057
Volume 5
Issue 2
Pages 57-68
Journal of Low Power Electronics and Applications, Vol 5, Iss 2, Pp 57-68 (2015)
Hiiekari, M, Teittinen, J, Koskinen, L, Turnquist, M J, Mäkipää, J, Rantala, A, Sopanen, M & Kaltiokallio, M 2015, ' A robust ultra-low voltage CPU utilizing timing-error prevention ', Journal of Low Power Electronics and Applications, vol. 5, no. 2, pp. 57-68 . https://doi.org/10.3390/jlpea5020057
To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all appli
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::59c06609dfadcb784b0149de8ea86e6b
https://aaltodoc.aalto.fi/handle/123456789/23851
https://aaltodoc.aalto.fi/handle/123456789/23851
Autor:
Tanja Kallio, Lauri Koskinen, Matthew Turnquist, Markus Hiienkari, Jani Makipaa, Elina Pohjalainen, Ruzica Jevtic
Publikováno v:
VLSIC
We introduce an ultra-low-energy system comprised of a prototype 1.55V Li-ion battery, fully integrated switched-capacitor (SC) DC-DC 3:1 converter, and a 32-bit RISC CPU with timing-error prevention (TEP). The DC-DC converter and CPU are manufacture
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d33fb0614a7ac27dd152b2c4991e0da0
http://juuli.fi/Record/0252814015
http://juuli.fi/Record/0252814015
Publikováno v:
Turnquist, M J, Hiienkari, M, Mäkipää, J & Koskinen, L 2015, A fully integrated self-oscillating switched-capacitor DC-DC converter for near-threshold loads . in Solid-State Circuits Conference (A-SSCC), 2015 IEEE Asian . IEEE Institute of Electrical and Electronic Engineers, pp. 1-4, IEEE Asian Solid-State Circuits Conference, Fujian, China, 9/11/15 . https://doi.org/10.1109/ASSCC.2015.7387441
A-SSCC
A-SSCC
We introduce a fully integrated step-down self-oscillating switched-capacitor DC-DC converter that delivers near-threshold (NT) output voltages. The converter is built in 28 nm UTBB FD-SOI and occupies 0.0104 mm2. Back-gate biasing is utilized to inc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c5168baadc3b5292cd90dfcc333445b6
http://juuli.fi/Record/0277364115
http://juuli.fi/Record/0277364115
Autor:
Markus Hiienkari, Mikko Kaltiokallio, Arto Rantala, Matti Sopanen, Jukka Teittinen, Lauri Koskinen, Matthew Turnquist, Jani Makipaa
Publikováno v:
Hiienkari, M, Teittinen, J, Koskinen, L, Turnquist, M, Kaltiokallio, M, Mäkipää, J, Rantala, A & Sopanen, M 2014, Ultra-wide voltage range 32-bit RISC CPU with timing-error prevention in 28nm CMOS . in Proceedings : SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014 ., 7028192, IEEE Institute of Electrical and Electronic Engineers, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2014, Millbrae, CA, United Kingdom, 6/10/14 . https://doi.org/10.1109/S3S.2014.7028192
To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all appli
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::971a004791ac588534123e7c3c0e8bdc
https://cris.vtt.fi/en/publications/b29dd3c0-5088-47be-a364-c15053d1cdda
https://cris.vtt.fi/en/publications/b29dd3c0-5088-47be-a364-c15053d1cdda
Autor:
Jani Makipaa, Olivier Billoint
Publikováno v:
ISCAS
Mäkipää, J & Billoint, O 2013, FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design? in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) . IEEE Institute of Electrical and Electronic Engineers, pp. 554-557, IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, China, 19/05/13 . https://doi.org/10.1109/ISCAS.2013.6571903
Mäkipää, J & Billoint, O 2013, FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design? in 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013) . IEEE Institute of Electrical and Electronic Engineers, pp. 554-557, IEEE International Symposium on Circuits and Systems, ISCAS 2013, Beijing, China, 19/05/13 . https://doi.org/10.1109/ISCAS.2013.6571903
Compared to BULK CMOS, FDSOI (Fully-Depleted Silicon-On-Insulator) introduces an ultra-thin buried oxide (BOX) layer and a dopant-free channel, which provides better performance and enhances ultra-low power (ULP) operation. To investigate benefits of