Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Jan-Willem Weijers"'
Autor:
Shiwei Wang, Marco Ballini, Xiaolin Yang, Chutham Sawigun, Jan-Willem Weijers, Dwaipayan Biswas, Nick Van Helleputte, Carolina Mora Lopez
Publikováno v:
IEEE Open Journal of the Solid-State Circuits Society, Vol 1, Pp 67-78 (2021)
This paper presents a scalable neural recording analog front-end architecture enabling simultaneous acquisition of action potentials, local field potentials, electrode DC offsets and stimulation artifacts without saturation. By combining a DC-coupled
Externí odkaz:
https://doaj.org/article/c040d51951d74eada46343f1d78310df
Autor:
Xiaolin Yang, Marco Ballini, Chutham Sawigun, Wen-Yang Hsu, Jan-Willem Weijers, Jan Putzeys, Carolina Mora Lopez
Publikováno v:
IEEE Journal of Solid-State Circuits. 58:949-960
Autor:
Dwaipayan Biswas, Carolina Mora Lopez, Shiwei Wang, Jan-Willem Weijers, Chutham Sawigun, Marco Ballini, Xiaolin Yang, Nick Van Helleputte
Publikováno v:
IEEE Open Journal of the Solid-State Circuits Society. 1:67-78
This paper presents a scalable neural recording analog front-end architecture enabling simultaneous acquisition of action potentials, local field potentials, electrode DC offsets and stimulation artifacts without saturation. By combining a DC-coupled
Autor:
Xiaolin Yang, Marco Ballini, Chutham Sawigun, Wen-Yang Hsu, Jan-Willem Weijers, Jan Putzeys, Carolina Mora Lopez
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Autor:
Dries Braeken, Carl Van Den Bulcke, Veerle Reumers, Shiwei Wang, Nick Van Helleputte, Hosung Chun, Andrea Firrincieli, Jan Putzeys, Jan-Willem Weijers, Carolina Mora Lopez, Laurent Berti
Publikováno v:
IEEE Journal of Solid-State Circuits. 53:3076-3086
Multi-electrode arrays (MEAs) are a candidate technology to screen cardiotoxicity in vitro because they enable noninvasive recording of cardiac beating rate, electrical field potential duration, and other parameters. In this paper, we present an acti
Autor:
Ilse Vos, Liesbet Van der Perre, Yanxiang Huang, Steven Dupont, Andy Dewilde, Meng Li, Veerle Derudder, Wim Van Thillo, Maxim Rykunov, Peter Debacker, Jan-Willem Weijers
Publikováno v:
A-SSCC
The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of transformation towards 5G. An energy efficient 18Gbps LDPC decoder based on LDPC ASIP with half layer paralleled architecture is proposed. The feasibility o
Autor:
Mattias Desmet, Hans Cappelle, Veerle Derudder, I. Vos, A.M. AbdelHamid, Antoine Dejonghe, L. Van der Perre, S. Singirikonda, Lieven Hollevoet, Frederik Naessens, S. O'Loughlin, Praveen Raghavan, Jan-Willem Weijers, Steven Dupont, L. Folens
Publikováno v:
2010 Symposium on VLSI Circuits.
This paper describes the implementation of a flexible Turbo and LDPC outer modem engine which is capable of supporting the WiFi(802.11n), WiMax(802.16e) and 3GPPLTE standard on the same hardware resources. The chip is implemented in a 65nm CMOS techn
Autor:
T. Schuster, Miguel Glassee, A. C. H. Ng, Jan-Willem Weijers, Bruno Bougard, L. Van der Perre
Publikováno v:
CODES+ISSS
Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require handheld platforms to shift from sets of multiple application specific
Autor:
A. Giulietti, Steven Dupont, Veerle Derudder, Bruno Bougard, Jan-Willem Weijers, L. Van der Perre
Publikováno v:
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).
Turbo coding has reached the step in which its astonishing coding gain is already being proven in real applications. Moreover, its applicability to future broadband communications systems is starting to be investigated. In order to be useful in this
Autor:
Veerle Derudder, L. Van der Perre, Lieven Hollevoet, Bruno Bougard, Jan-Willem Weijers, H. De Man, F. Catthoor, Steven Dupont, Rudy Lauwereins, A. Giulietti
Publikováno v:
IEEE international solid-state circuits conference
A 6 to 75.6Mb/s turbo CODEC with block size from 32 to 432, code rate from 1/3 to 3/4, 5.35/spl mu/s/block decoding latency and up to 8.25dB coding gain is described. This IC is fabricated in a 0.18/spl mu/m process and has a core area of 7.16mm/sup