Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Jan Malburg"'
Publikováno v:
DDECS
Current embedded systems are increasingly using networks, be it for connecting different components or in form of Network on Chips in case of Multi-Processor System on Chip. Knowing the performance parameters of those networks, especially in case tha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bc8c7a0ca028df205680e42effc79674
https://elib.dlr.de/128841/
https://elib.dlr.de/128841/
Autor:
Tara Ghasempouri, Goerschwin Fey, Jan Malburg, Graziano Pravadelli, Jaan Raik, Alessandro Danese
Publikováno v:
VLSI-SoC
Several approaches exist for specification mining of hardware designs, both at the RTL and system levels (e.g, TLM). These approaches mine assertions that specify the behavior of the design. Some of the techniques require the source code itself while
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::6eed2c82b2c267b038de7060e11d5b48
http://hdl.handle.net/11562/1001101
http://hdl.handle.net/11562/1001101
Publikováno v:
ISMVL
Guaranteed response times are crucial for control applications. Analyzing the communication latency, i.e., the time needed to transfer data from one end-point to another, in complex on-chip communication architectures is hard. In this paper, we forma
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4e8858cf66dbd9e03cc8ea0e044b583e
https://doi.org/10.1109/ismvl.2018.00020
https://doi.org/10.1109/ismvl.2018.00020
Autor:
Tino Flenker, Jan Malburg, Görschwin Fey, Massimo Violante, Serhiy Avramenko, Matteo Sonza Reorda
Publikováno v:
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
ISVLSI
ISVLSI
Fault injection and fault simulation are a typical approach to analyze the effect of a fault on a hardware/software system. Often fault injection is done on abstract models of the system either to retrieve early results when no implementation is avai
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::360ed0c7c114dfd1ccd9557d26dbc28d
https://elib.dlr.de/114577/
https://elib.dlr.de/114577/
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33:1886-1899
The complexity of modern chips is rapidly increasing. To fulfill tight time-to-market constraints, more and more blocks from previous designs are reused or third party IP blocks are licensed. However, such blocks are often only poorly documented maki
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2484b90242a31ce130bdde0faf331253
https://doi.org/10.1109/tcad.2014.2360462
https://doi.org/10.1109/tcad.2014.2360462
Autor:
Jan Malburg, Gordon Fraser
Publikováno v:
Software Testing, Verification and Reliability. 24:472-495
Many modern automated test generators are based on either metaheuristic search techniques or use constraint solvers. Both approaches have their advantages, but they also have specific drawbacks: Search-based methods may get stuck in local optima and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66f881dbce78acd3cac5c7d17307ecb2
https://doi.org/10.1002/stvr.1508
https://doi.org/10.1002/stvr.1508
Fault localization in RTL design using dynamic dependency graphs.Reverse debugging for RTL designs.Scalable and fast approach applicable to large designs.Manual debugging effort can be reduced by more than 50ź%. Display Omitted Debugging is a time c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bcf5bf7ac813c29f2c890643e0187bca
https://elib.dlr.de/110227/
https://elib.dlr.de/110227/
Autor:
Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon ter Braak, Sergei Devadze, Goerschwin Fey, Maksim Jenihhin, Artur Jutman, Kerkoff, Hans G., Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao
Publikováno v:
TU Graz
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::affc60f14e638fb6890cc11efda7ef50
https://elib.dlr.de/105923/
https://elib.dlr.de/105923/
Publikováno v:
DDECS
In modern chip design, many different blocks are assembled in a single chip. Normally, these blocks have been written by different developers or even licensed from other companies. Correctly connecting all blocks is a tedious task. State of the art t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::b58bb9f5a050d36323058377dd16e6b4
https://elib.dlr.de/93846/
https://elib.dlr.de/93846/