Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Jan Hoogerbrugge"'
Autor:
Surendra Guntur, Phillip Christie, Ghiath Al-Kadi, Anirban Lahiri, Clemens Wüst, Andrei Terechko, A. Kumar, Marc Duranton, Jan Hoogerbrugge, Axel Nackaerts
Publikováno v:
The Lens
Multicore architectures provide scalable performance with a lower hardware design effort than single core processors. Our article presents a design methodology and an embedded multicore architecture, focusing on reducing the software design complexit
Publikováno v:
FPL
This paper describes the system architecture, design methodology and subsequent FPGA mapping of a millimeter wave digital baseband for wireless communication in the 60GHz spectral band. The baseband is designed to be compliant with the 802.11ad Singl
Autor:
Jan Hoogerbrugge
Publikováno v:
ICCD
Power consumption of digital baseband processing of a wireless receiver can be reduced by operating the circuits at a reduced voltage where setup timing errors occur occasionally in a controlled way. One of the challenges is then to estimate the BER
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::cf0a1ee54cbf5c7dee61ddd2658af1fc
Autor:
Alex Ramirez, Cor Meenderinck, Mauricio Alvarez, Ben Juurlink, Mateo Valero, Arnaldo Azevedo, Jan Hoogerbrugge, Andrei Terechko
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783642245671
Developing parallel applications that can harness and efficiently use future many-core architectures is the key challenge for scalable computing systems. We contribute to this challenge by presenting a parallel implementation of H.264 that scales to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::69af10d420f2f686be0b6a86c47bc321
https://doi.org/10.1007/978-3-642-24568-8_6
https://doi.org/10.1007/978-3-642-24568-8_6
Autor:
Jan Hoogerbrugge, Andrei Terechko
Publikováno v:
Transactions on High-Performance Embedded Architectures and Compilers III ISBN: 9783642194474
We describe a multicore system targeting media processing applications where the cores are multithreaded. The multithreaded cores use a new type of multithreading that we call Subset Static Interleaved (SSI) multithreading. SSI multithreading combine
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0ac21c6dbaba37fcdc81f963b92883af
https://doi.org/10.1007/978-3-642-19448-1_9
https://doi.org/10.1007/978-3-642-19448-1_9
Autor:
Andrei Terechko, Marc Duranton, Onno Eerenberg, Ghiath Al-Kadi, Jan Hoogerbrugge, Surendra Guntur
Publikováno v:
2010 Digest of Technical Papers International Conference on Consumer Electronics (ICCE).
This paper presents a method to parallelize the meandering based 3D recursive search (3DRS) motion estimation algorithm used in scan-rate up-conversion. The proposed algorithm is scalable and can easily be mapped to multiple processing units such as
Publikováno v:
Processor and System-on-Chip Simulation ISBN: 9781441961747
Multicore architectures provide scalable performance with a hardware design effort lower than for a single core processor with similar performance. This chapter presents a design methodology and an embedded multicore architecture focusing on boosting
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4a960dca036e211cf24ab52636cc055
https://doi.org/10.1007/978-1-4419-6175-4_16
https://doi.org/10.1007/978-1-4419-6175-4_16
Autor:
Arnaldo Azevedo, Cor Meenderinck, Ben Juurlink, Alex Ramirez, Mauricio Alvarez, Jan Hoogerbrugge, Andrei Terechko
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
High Performance Embedded Architectures and Compilers ISBN: 9783540929895
HiPEAC
HiPEAC 2009-High Performance and Embedded Architectures and Compilers
HiPEAC 2009-High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_29⟩
Recercat. Dipósit de la Recerca de Catalunya
instname
Universitat Politècnica de Catalunya (UPC)
High Performance Embedded Architectures and Compilers ISBN: 9783540929895
HiPEAC
HiPEAC 2009-High Performance and Embedded Architectures and Compilers
HiPEAC 2009-High Performance and Embedded Architectures and Compilers, Jan 2009, Paphos, Cyprus. ⟨10.1007/978-3-540-92990-1_29⟩
Recercat. Dipósit de la Recerca de Catalunya
instname
In previous work the 3D-Wave parallelization strategy was proposed to increase the parallel scalability of H.264 video decoding. This strategy is based on the observation that inter-frame dependencies have a limited spatial range. The previous result
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3289c2d393b897126f8adb8cd1f016e9
Autor:
Lex Augusteijn, Jan Hoogerbrugge
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540672630
CC
CC
The performance of a Java Virtual Machine (JVM) interpreter running on a very long instruction word (VLIW) processor can be improved by means of pipelining. While one bytecode is in its execute stage, the next bytecode is in its decode stage, and the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c9d7a03516cca539f5b577c961689db0
https://doi.org/10.1007/3-540-46423-9_3
https://doi.org/10.1007/3-540-46423-9_3
Publikováno v:
Philips Research ISBN: 9781402034534
Systems-on-Chip (SoC) of the new generation will be extremely complex devices, composed from complex subsystems, relying on abstraction from implementation details. These chips will support the execution of a mix of concurrent applications that are n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b4a3ae726bc91d183eb8e91d68042e1
https://doi.org/10.1007/1-4020-3454-7_3
https://doi.org/10.1007/1-4020-3454-7_3