Zobrazeno 1 - 10
of 264
pro vyhledávání: '"Jan Craninckx"'
Autor:
Linkun Wu, David San Segundo Bello, Philippe Coppejans, Jan Craninckx, Andreas Süss, Maarten Rosmeulen, Piet Wambacq, Jonathan Borremans
Publikováno v:
Sensors, Vol 18, Iss 11, p 3683 (2018)
This paper presents an in-situ storage topology for ultra-high-speed burst mode imagers, enabling low noise operation while keeping a high frame depth. The proposed pixel architecture contains a 4T pinned photodiode, a correlated double sampling (CDS
Externí odkaz:
https://doaj.org/article/a045ba1c46c54f069fdfa9319632fb4e
Publikováno v:
IEEE Journal of Solid-State Circuits. 58:1586-1596
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c44f842db4fc19d83075b32b911ec68c
https://doi.org/10.1109/jssc.2022.3219060
https://doi.org/10.1109/jssc.2022.3219060
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:1997-2010
This article presents a 55-63-GHz fundamental multicore voltage-controlled oscillator (VCO) in a 28-nm bulk CMOS process. The single-core VCO utilizes stacking and magnetic coupling of two NMOS-based resonators, which increases the tank energy for ph
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f393736f3dcac1535fd7f46c7d713659
https://doi.org/10.1109/jssc.2022.3165654
https://doi.org/10.1109/jssc.2022.3165654
Autor:
Anirudh Kankuppe, Sehoon Park, Kristof Vaesen, Dae-Woong Park, Barend Van Liempd, Siddhartha Sinha, Piet Wambacq, Jan Craninckx
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:1982-1996
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b862e25fa7e2e8b45c9210ef61b15c11
https://doi.org/10.1109/jssc.2022.3165429
https://doi.org/10.1109/jssc.2022.3165429
Autor:
Lucas Moura Santana, Ewout Martens, Jorge Lagos, Benjamin Hershberg, Piet Wambacq, Jan Craninckx
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:2068-2077
This article presents a delta sigma modulator (DSM) analog to digital (ADC) that uses ring amplifiers as integrators to relax speed and efficiency bottlenecks in discrete-time (DT) oversampled ADCs. Its multi-bit quantizer is based on split source (S
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a6ce5ef4b41042e8947e29a4f4a9b510
https://doi.org/10.1109/jssc.2022.3163819
https://doi.org/10.1109/jssc.2022.3163819
Autor:
Jan Craninckx, Lai Wei, Ewout Martens, Yan Zhu, Chi-Hang Chan, Rui P. Martins, Zihao Zheng, Jorge Lagos
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:1673-1683
This article presents a single-channel 3.3-GS/s 6-b pipelined analog-to-digital converter (ADC), which features a post-amplification residue generation (PARG) scheme, linearized dynamic amplifier (DA), and on-chip calibration to achieve a high speed,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b9bd157b19702aacea8243443db74f09
https://doi.org/10.1109/jssc.2021.3096938
https://doi.org/10.1109/jssc.2021.3096938
Publikováno v:
2023 IEEE Custom Integrated Circuits Conference (CICC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4e4a441847520e8154ad21b4984b5f2
https://doi.org/10.1109/cicc57935.2023.10121250
https://doi.org/10.1109/cicc57935.2023.10121250
Autor:
Jorge Lagos, Nereo Markulic, Benjamin Hershberg, Davide Dermit, Mithlesh Shrivas, Ewout Martens, Jan Craninckx
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:1112-1124
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a243fb4e887d0206e810dd7a04c621c5
https://doi.org/10.1109/jssc.2021.3133829
https://doi.org/10.1109/jssc.2021.3133829
Autor:
Chris Van Hoof, Georges Gielen, Jan Craninckx, Beatrice Miccoli, Xiaohua Huang, Carolina Mora Lopez, Marco Ballini, Nick Van Helleputte, Shiwei Wang
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 69:804-808
An ultra-small-area, low-power analog front-end (AFE) for high-density neural recording is presented in this paper. It features an 11-bit incremental delta-sigma analog-to-digital converter (σ ADC) enhanced with an offset-rejecting event-driven inpu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::841a41aaceb9b3cee968527d5ed98995
https://doi.org/10.1109/tcsii.2021.3111257
https://doi.org/10.1109/tcsii.2021.3111257
Autor:
Pratap Tumkur Renukaswamy, Kristof Vaesen, Nereo Markulic, Veerle Derudder, Dae-Woong Park, Piet Wambacq, Jan Craninckx
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d5d0d3fdaeaa0a12812fe738c20e7612
https://doi.org/10.1109/isscc42615.2023.10067404
https://doi.org/10.1109/isscc42615.2023.10067404