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of 11
pro vyhledávání: '"Jan Ackaert"'
Autor:
Evert Visker, Serge Vanhaelemeersch, David Huls, Karthik Muga, Alexandre La Grappe, Augusto Redolfi, Lan Peng, Anne Lauwers, Jan Ackaert
Publikováno v:
2021 IEEE 71st Electronic Components and Technology Conference (ECTC).
Patterning on Si with high aspect ratio trenches by spin-coating of photoresist faces significant challenges. The desire to maintain a good thickness uniformity of resist on wafer surface, to minimize any residue inside deep trenches, as well as enab
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 4:240-247
During the wafer fabrication process, wafers warp into different kinds of shapes, such as spherical, cylindrical, or saddles. These wafers may exhibit a bistable state, that is, if we apply a certain amount of pressure, they snap into another state.
Publikováno v:
ICICDT
Deformations of metal interconnects, cracks in interlayer dielectrics and passivation layers in combination with plastic packaging are still a major reliability concern for integrated circuit power semiconductors. In order to describe and understand
Autor:
Joseph Rayhem, Paul Hendrickx, B. Desoete, Jan Van Houdt, Sylvie Boonen, Mike Thomason, Jan Ackaert, Jagdish Prasad, Robin Degraeve, A. Lowe, Luc Haspeslagh, T. Yao
Publikováno v:
Solid-State Electronics. 48:1911-1915
A critical problem of floating gate type nonvolatile memories (FG-NVMs) used in flash memories or EEPROMs is anomalous charge loss which leads to threshold voltage (Vt) shifts on a time scale of months or years at room temperature. The number of thes
Publikováno v:
ICICDT
Deformations of metal interconnects, cracks in interlayer dielectrics and passivation layers in combination with plastic packaging are still a major reliability concern for integrated circuit power semiconductors. In order to describe and understand
Publikováno v:
2011 IEEE International Conference on IC Design & Technology.
Deformations of metal interconnects, cracks in interlayer dielectrics and passivation layers in combination with plastic-packaging are still a major reliability concern for integrated circuit power semiconductors. In order to describe and understand
Autor:
Jan Ackaert, B. Greenwood
Publikováno v:
2010 IEEE International Conference on Integrated Circuit Design and Technology.
ESD problems are commonly thought to be an electrostatic discharge event through the device pins. All known models like HBM, MM, CDM are based on this assumption. During assembly discharge into devices, directly into the surface is also well known. P
Publikováno v:
ECS Meeting Abstracts. :705-705
not Available.
Conference
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