Zobrazeno 1 - 10
of 12
pro vyhledávání: '"James Karp"'
Autor:
Phoumra Tan, Marko Simicic, Yoojin Ban, Artemisia Tsiara, Peter De Heyn, Xin Wu, Michael J. Hart, Joris Van Campenhout, Kristof Croes, James Karp, Dimitri Linten, Shih-Hung Chen, Jonathan Chang, Dean Tsaggaris
Publikováno v:
2021 43rd Annual EOS/ESD Symposium (EOS/ESD).
ESD robustness for self-protected advanced Silicon photonic components integrated into optical interposers is reported, including industry-first CDM data. HBM performance in reverse bias polarity is shown to be the limiting factor and is correlated t
Publikováno v:
IEEE Transactions on Nuclear Science. 65:217-222
Increased sensitivity of FinFET technology to single-event latch-up (SEL) was found during 64-MeV proton beam accelerated testing and confirmed with neutron beam experiments. TCAD simulations demonstrate that the $3\times $ shallower trench isolation
Publikováno v:
ISQED
The proposed verification methodology enables designers to meet a maximum resistance specification for the well taps routing. Key strengths of the flow are: automatic identification of both well taps and VDD/VSS grid; comparison of the extracted resi
Autor:
Anda Mocuta, James Karp, Shih-Hung Chen, Mirko Scholz, Guido Groeseneken, D. Linten, Naoto Horiguchi, Ming-Dou Ker, Roman Boschke, M. Hart, C.-T. Dai, Geert Hellings
Publikováno v:
2017 IEEE International Reliability Physics Symposium (IRPS).
Latchup (LU) had been considered to be less important in advanced CMOS technologies. However, I/O interface and analog applications can still operate at high voltage (e.g., 1.8V or 3.3V) in sub-20nm bulk FinFET technologies. LU threats are never elim
Autor:
Larry Horwitz, Michael J. Hart, Vassili Kireev, Matthew Hogan, Mohammed Fakhruddin, James Karp
Publikováno v:
MWSCAS
Custom ESD protection without increasing loading capacitance is demonstrated for transmitter (TX) and receiver (RX) pins of the Xilinx Zynq UltraScale+ Microprocessor System-on-Chip (MPSoC) transceivers. Optimized T-coil cancellation was applied at a
Autor:
Mohammed Fakhruddin, Phoumra Tan, James Karp, Rawat Mini, Vassili Kireev, Dean Tsaggaris, Michael J. Hart
Publikováno v:
2016 IEEE International Reliability Physics Symposium (IRPS).
Methodology proposed that relates 200V CDM voltage specification of S20.20-2014 standard to a realistic 100–200mA CDM peak current for inter-die interfaces. Tribology is considered to be the source of charge accumulation on the bare die during 3D/2
Publikováno v:
Journal of Physics D: Applied Physics. 40:2143-2149
Barrier parameters of a thermally grown SiOx gate oxide are derived by relating the SIMS oxygen concentration profile to the barrier height. Even in the simple analytical form such a graded barrier model agrees with the tunnelling current and its vol
Publikováno v:
2015 IEEE Radiation Effects Data Workshop (REDW).
The single-event response vs. temperature and Vcc supply voltage of the 20nm Kintex UltraScale FPGA is characterized using a 64 MeV proton beam as proxy for atmospheric neutron. Single-event upset and multi-bit upset results are presented.
Publikováno v:
2015 IEEE Radiation Effects Data Workshop (REDW).
The single-event response of Xilinx 20nm UltraScale Kintex FPGA is characterized using neutron, 64 MeV proton, thermal neutron and alpha foil irradiation sources. Single-event upset and multi-bits upset results are presented.
Publikováno v:
Journal of Applied Physics. 95:2490-2494
Degradation and time dependent breakdown of SiO2 gate oxides are discussed based on the Anderson–Mott theory of amorphous solids with dangling bonds as diamagnetic “negative Hubbard U” centers. Negative-U dangling bonds in the oxide are either