Zobrazeno 1 - 10
of 41
pro vyhledávání: '"Jai-Hoon Sim"'
Autor:
Jai-Hoon Sim, Kyu-Chan Lee, Nam-jong Kim, Soo-In Cho, Hongil Yoon, Byung-sik Moon, Dong-ryul Ryu, Seung-Moon Yoo, Changhyun Kim, Sang-Bo Lee, Keum-Yong Kim, Jei-Hwan Yoo
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:642-648
This paper describes several new circuit design techniques for low V/sub CC/ regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (/spl Delta/V/sub BL/) as well as the V/sub GS/ margin by boosti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c07d12644c9745a83e883124a2740643
https://doi.org/10.1109/4.568824
https://doi.org/10.1109/4.568824
Autor:
Keum-Yong Kim, Ejaz Haq, Kye-Hyun Kyung, Kinam Kim, Bok-Moon Kang, Moon-Hae Son, Chang-Hyun Kim, Hyung-Kyu Lim, Soo-In Cho, K. H. Lee, Jai-Hoon Sim, Sang-Bo Lee, Jae-Gwan Park, Jong-Woo Park, Jung-Hwa Lee, Seung-Moon Yoo, Jei-Hwan Yoo, Joungho Kim, Jinman Han, Byung-sik Moon, Kang-yoon Lee, Kyu-Chan Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:1635-1644
This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe8f35bf377499dd5f1a434eea274fb8
https://doi.org/10.1109/jssc.1996.542308
https://doi.org/10.1109/jssc.1996.542308
Autor:
Jai-Hoon Sim
Publikováno v:
IEEE Transactions on Electron Devices. 42:864-869
In order to evaluate the velocity overshoot phenomenon in the deep submicron MOS devices, the energy balance equation should be incorporated with the drift-diffusion equation that includes thermoelectric diffusion. This paper presents an analytical c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::27f2d13b806d553b75f6d9dd35028de2
https://doi.org/10.1109/16.381981
https://doi.org/10.1109/16.381981
Publikováno v:
IEEE Transactions on Electron Devices. 42:1495-1502
In this paper, we introduce the Si-SiGe narrow bandgap-source (NBS) SOI device structure in order to improve the low drain-to-source breakdown voltage (V/sub BD/) in ultra-thin SOI devices. Reducing the potential barrier of valence band between sourc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5157a8f267be77f6bc35383293a2df0c
https://doi.org/10.1109/16.398664
https://doi.org/10.1109/16.398664
Autor:
Christopher S. Putnam, K. Duncan, Lawrence F. Wagner, Yue Liang, Sungjae Lee, Anthony I. Chou, Y. Deng, Murshed M. Chowdhury, Kai Zhao, Brian Johnson, Brian J. Greene, William K. Henson, Rainer Thoma, Dustin K. Slisher, R. Rupani, Scott K. Springer, J. Johnson, D. Daley, C. Wermer, Jean-Olivier Plouchart, Edward P. Maciejewski, Y. Wang, Jie Deng, Hongmei Li, Amit Kumar, Jai-Hoon Sim, Paul A. Hyde, Richard Q. Williams, S.H. Ku, A. Sutton, Shreesh Narasimha, Daeik Daniel Kim
Publikováno v:
2012 Symposium on VLSI Technology (VLSIT).
We demonstrate advanced modeling and optimization of 32nm high-K metal gate (HKMG) SOI CMOS technology for high-speed digital and RF/analog system-on-chip applications. To enable high-performance RF/analog circuit design, we present challenging devic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0856e026fef8b67a3ab657c495e22e07
https://doi.org/10.1109/vlsit.2012.6242498
https://doi.org/10.1109/vlsit.2012.6242498
Publikováno v:
Solid-State Electronics. 37:459-462
In this paper, a fully analytical back-gate bias effect model for n-channel silicon MESFET devices is presented. As verified by the PISCES results, the analytical n-channel silicon MESFET back-gate bias effect model provides a good accuracy in the in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c86bb4e1afe9ce79e4bd122b58127f60
https://doi.org/10.1016/0038-1101(94)90012-4
https://doi.org/10.1016/0038-1101(94)90012-4
Autor:
Jai-Hoon Sim, Jui-Chang Kuo
Publikováno v:
Solid-State Electronics. 37:463-472
This paper presents a closed-form analytical delayed-turn-on model for accumulation-type ultra-thin SOI PMOS devices operating in the “delayed-turn-on” regime at liquid nitrogen temperature. As verified by the low-temperature PISCES results [Kuo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e49e9fe43b1b4c5510984b50ee434fcd
https://doi.org/10.1016/0038-1101(94)90013-2
https://doi.org/10.1016/0038-1101(94)90013-2
Publikováno v:
Solid-State Electronics. 36:1349-1352
This paper reports an analytical threshold voltage model for SiGe-channel P&IOS devices. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical formula, wit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::f4e500163045bffe1ef6baffae695b9b
https://doi.org/10.1016/0038-1101(93)90176-q
https://doi.org/10.1016/0038-1101(93)90176-q
Autor:
James B. Kuo, Jai-Hoon Sim
Publikováno v:
Solid-State Electronics. 36:717-721
This paper reports a unique delayed-turn-on behavior in an accumulation-type SOI PMOS device operating at 77 K based on the low-temperature PISCES simulation [J.B. Kuo and Y.W. Chen, IEEE Trans. Electron. Devices ED-39 , 348 (1992)]. As compared to t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7f2b7515768de1d5c5c9e18eb3a1fa16
https://doi.org/10.1016/0038-1101(93)90240-q
https://doi.org/10.1016/0038-1101(93)90240-q
Autor:
Jai-Hoon Sim, James B. Kuo
Publikováno v:
Solid-State Electronics. 36:793-797
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::74abe0fcb10b18a1d0ffe83eb91106ad
https://doi.org/10.1016/0038-1101(93)90252-l
https://doi.org/10.1016/0038-1101(93)90252-l