Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Jagadish Dasarahalli Narasimaiah"'
Publikováno v:
Cybernetics and Systems. :1-29
Publikováno v:
IET Circuits, Devices & Systems. 12:671-680
In this work, design technique and analysis of low-energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. A dual capacitor array (CA) generates a digital-to-analogue reference voltage with increas
Publikováno v:
IET Circuits, Devices & Systems. 12:249-255
In this study, a design technique for low-energy consumption and area-efficient successive approximation register analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion equivalent voltage is acquired utilising passive sharin