Zobrazeno 1 - 10
of 25
pro vyhledávání: '"Jafar Savoj"'
Autor:
Zhaoyin Daniel Wu, Kenny Hsieh, Wayne Y. Fang, Didem Turker, Jose Anup P, Jafar Savoj, Declan Carey, Yohan Frans, Hesam Amir-Aslanzadeh, Marc Erett, Jay Im, Ken Chang, Adebabay M. Bekele, Parag Upadhyaya
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:1932-1944
This paper describes a 0.5–16.3 Gb/s fully adaptive wireline transceiver embedded in 20 nm CMOS FPGA. The receiver utilizes bandwidth adjustable CTLE and adjustable output capacitance at the AGC to support wide range of channel loss profiles. A mod
Autor:
Xuewen Jiang, Kenny Hsieh, Jason Gong, Didem Turker, Siok Wei Lim, Jose Anup P, Jay Im, Arianne Roldan, Fu-Tai An, Vassili Kireev, Ken Chang, Parag Upadhyaya, Daniel Wu, Jafar Savoj
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:2582-2594
This paper describes the design of a 0.5-6.6 Gb/s fully-adaptive low-power quad transceiver embedded in low-leakage 28 nm CMOS FPGAs. Integration techniques enable the utilization of the transceiver in FPGAs with both wire-bond and flip-chip packages
Publikováno v:
IEEE Journal of Solid-State Circuits. 46:2739-2744
The 34 papers in this special issue can be divided into several groups: analog papers; data converter papers; RF papers; wireless communication papers; and wireline communication papers.
Autor:
Metha Jeeradit, Vladimir Stojanovic, Ravi Kollipara, Amir Amirkhany, Jafar Savoj, Aliazam Abbasfar, Bruno W. Garlepp, Mark Horowitz
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:999-1009
A 24 Gb/s transmitter employs a digital linear equalizer and a 12 GS/s 8-bit digital-to-analog converter (DAC). Implemented in a 90 nm CMOS technology, the transmitter can be programmed to support a variety of communication modes including 4-channel
Autor:
Bruce Xu, Ade Bekele, Jafar Savoj, Hiva Hedayati, Fu-Tai An, Parag Upadhyaya, Hesam Aslanzadeh, Jose Anup P, Yohan Frans, Toan Pham, Stanley Chen, Didem Furker, Daniel Wu, Siok Wei Lim, Jay Im, Ken Chang
Publikováno v:
ISSCC
The introduction of high-speed backplane transceivers inside FPGAs has addressed critical issues such as the ease in scalability of performance, high availability, flexible architectures, the use of standards, and rapid time to market. These have bee
Publikováno v:
2014 IEEE International Electron Devices Meeting.
This paper studies the interaction between devices in advanced CMOS processes and the analog circuits used in high-speed transceivers. It describes the impact of variation on the design with both active and passive devices, and devises circuit techni
Autor:
Jay Im, Ken Chang, Wayne Fang, Declan Carey, Hesam Aslanzadeh, Jose Anup P, Yohan Frans, Kenny Hsieh, Jafar Savoj, Didem Turker, Parag Upadhyaya, Marc Erett, Daniel Wu
Publikováno v:
CICC
Autor:
Ali M. Niknejad, Parag Upadhyaya, Stanley Chen, Jafar Savoj, Ken Chang, Jun-Chau Chien, Wayne Fang, Howard Jung
Publikováno v:
ISSCC
High-speed transceivers embedded inside FPGAs require software-programmable clocking circuits to cover a wide range of data rates across different channels [1]. These transceivers use high-frequency PLLs with LC oscillators to satisfy stringent jitte
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:1683-1685
Publikováno v:
ISSCC
Technology awareness and modeling is important in all areas of mixed-signal and RF design. This forum intends to provide a holistic overview and discussion spanning a variety of important topics in device modeling, reliability and simulation in next-