Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Jaekwang Yun"'
Publikováno v:
IEEE Access, Vol 11, Pp 30555-30561 (2023)
Duty-cycle distortion may occur due to variations in the process, voltage, and temperature, or if the clock signal passes through clock buffers. To compensate duty-cycle distortion, a digital duty-cycle corrector (DCC) with counter-based half-cycle d
Externí odkaz:
https://doaj.org/article/2d870e167b0442a287836ab67c224b72
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 69:4208-4212
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4697f90081a0dfbad604b930baf4480d
https://doi.org/10.1109/tcsii.2022.3188037
https://doi.org/10.1109/tcsii.2022.3188037
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 69:1125-1134
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a4017f74bca09df5eee096e20f418d00
https://doi.org/10.1109/tcsi.2021.3123753
https://doi.org/10.1109/tcsi.2021.3123753
Autor:
Jaekwang Yun, Han-Gon Ko, Deog-Kyoon Jeong, Soyeong Shin, Chan-Ho Kye, Hae-Kang Jung, Suhwan Kim, Sang Yoon Lee, Doobock Lee
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 67:1814-1818
This brief presents a power- and area-efficient forwarded-clock (FC) receiver with a delay-locked loop (DLL)-based self-tracking loop for unmatched memory interfaces. In the proposed FC receiver, the self-tracking loop is composed of two-stage cascad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dcbfcb831d99b091cdb2f727eb83a3c3
https://doi.org/10.1109/tcsii.2019.2957042
https://doi.org/10.1109/tcsii.2019.2957042
Autor:
Deog-Kyoon Jeong, Joo-Hyung Chae, Jaekwang Yun, Soyeong Shin, Suhwan Kim, Han-Gon Ko, Sang Yoon Lee
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 67:1735-1739
Skews between data and strobe signals can occur in HBM transceivers due to process and voltage variations across the base die. Skew compensation is introduced into the deserializers of our quarter-rate single-ended receiver for next-generation unmatc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::277723eb641e6b9fb081806a0816bbd3
https://doi.org/10.1109/tcsii.2019.2947296
https://doi.org/10.1109/tcsii.2019.2947296
Autor:
Yong-Un Jeong, Suhwan Kim, Jihwan Park, Joo-Hyung Chae, Jaekwang Yun, Hyunjoong Lee, Mino Kim
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 67:1589-1593
This brief presents a 9Gb/s transmitter for intra-panel interfaces, with dual-loop calibration and a 2D binary-segmented driver. The dual-loop calibration during the training period compensates the transmitter output for the variations in operating c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1707e0ecf7a80a78695b815965a07bae
https://doi.org/10.1109/tcsii.2020.3013420
https://doi.org/10.1109/tcsii.2020.3013420
Publikováno v:
2022 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce7741b4a25f6284bccf9f41b628ea2b
https://doi.org/10.1109/isscc42614.2022.9731653
https://doi.org/10.1109/isscc42614.2022.9731653
Publikováno v:
A-SSCC
This paper proposes a fractional-N phase-locked loop (PLL) with a transition-detection DAC (TD-DAC) for jitter reduction. By introducing a TD-DAC, the sigma-delta modulator (SDM) quantization error of the PLL is compensated, and its overall jitter pe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f6f55d2f218db1060450331165c3cea9
https://doi.org/10.1109/a-sscc48613.2020.9336144
https://doi.org/10.1109/a-sscc48613.2020.9336144
Publikováno v:
ISLPED
The increasing data rate of serial links makes it difficult to match timing constraints of serializers in transmitters. Delay compensation clock buffers can alleviate this issue by matching the timing between data and clock. However, these buffers co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1439a586519d6ab08aa07130c5b75ce4
https://doi.org/10.1109/islped.2019.8824879
https://doi.org/10.1109/islped.2019.8824879
Autor:
Suhwan Kim, Soyeong Shin, Sang Yoon Lee, Doobock Lee, Jaekwang Yun, Han-Gon Ko, Chan-Ho Kye, Deog-Kyoon Jeong, Hae-Kang Jung
Publikováno v:
VLSI Circuits
This paper presents a data (DQ) receiver for HBM3 with a self-tracking loop that tracks a phase skew between DQ and data strobe (DQS) due to a voltage or thermal drift. The self-tracking loop achieves low power and small area by utilizing an analog-a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4dbda1ab4910b452476f04dba88d8f8f
https://doi.org/10.23919/vlsic.2019.8778082
https://doi.org/10.23919/vlsic.2019.8778082