Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Jaehwa Kwak"'
Autor:
Jaehwa Kwak, Stevo Bailey, Nandish Mehta, John Wright, Pi-Feng Chiu, Daniel Dabbelt, Krste Asanovic, Borivoje Nikolic, Vighnesh Iyer, Colin Schmidt, Ben Keller
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:2721-2725
This work demonstrates a dual-core RISC-V system-on-chip (SoC) with integrated fine-grain power management. The 28-nm fully depleted silicon-on-insulator (FD-SOI) SoC integrates switched-capacitor voltage converters and 4-Gb/s off-chip serial links.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e2b7c77d0fb8817145a3f6feb3c238b3
https://doi.org/10.1109/tvlsi.2020.3030243
https://doi.org/10.1109/tvlsi.2020.3030243
Publikováno v:
2021 IEEE 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::de56cefe9c37eeb542cfc977730500b3
https://doi.org/10.1109/sbac-pad53543.2021.00020
https://doi.org/10.1109/sbac-pad53543.2021.00020
Autor:
Po-Hung Chen, Hanh-Phuc Le, Brian Richards, Pi-Feng Chiu, Milovan Blagojević, Elad Alon, James Dunn, Nicholas Sutardja, Jaehwa Kwak, Ben Keller, Yunsup Lee, Palmer Dabbelt, Rimas Avizienis, Stevo Bailey, Andreia Cathelin, Alberto Puggelli, Andrei Vladimirescu, Brian Zimmer, Philippe Flatresse, Andrew Waterman, Colin Schmidt, Ruzica Jevtic, Martin Cochet, Krste Asanovic, Borivoje Nikolic
Publikováno v:
Integrated Circuits and Systems ISBN: 9783030394950
Improving the energy efficiency of processor systems-on-chip (SoCs) is key to improving their performance and utility. The FD-SOI silicon process enables integrated systems that can deliver dramatic improvements in energy efficiency through system in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::57d8006d43be18490af2e59525ebf897
https://doi.org/10.1007/978-3-030-39496-7_11
https://doi.org/10.1007/978-3-030-39496-7_11
Autor:
Jaehwa Kwak, Borivoje Nikolic
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:2368-2379
This work demonstrates a self-adjustable clock generator that closely tracks the voltage dependence of the critical path delay in a microprocessor. A tunable replica circuit (TRC) composed of inverter cells from the standard-cell library performs rea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f44d25ddc808327ed765f285d31e9785
https://doi.org/10.1109/jssc.2016.2582860
https://doi.org/10.1109/jssc.2016.2582860
Autor:
Andrew Waterman, Yunsup Lee, Alberto Puggelli, Philippe Flatresse, Po-Hung Chen, Brian Richards, Krste Asanovic, Ben Keller, Borivoje Nikolic, Steven Bailey, Elad Alon, Rimas Avizienis, Jaehwa Kwak, Ruzica Jevtic, Nicholas Sutardja, Hanh-Phuc Le, Pi-Feng Chiu, Brian Zimmer, Milovan Blagojevic
Publikováno v:
IEEE Journal of Solid-State Circuits, vol 51, iss 4
This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::470d51f062eff1134bbcee301abae8b7
https://doi.org/10.1109/jssc.2016.2519386
https://doi.org/10.1109/jssc.2016.2519386
Autor:
Krste Asanovic, Bora Nikolic, David A. Patterson, Yunsup Lee, Jaehwa Kwak, Andrew Waterman, Elad Alon, Ben Keller, Henry Cook, Ruzica Jevtic, Stevo Bailey, Alberto Puggelli, Brian Richards, Pi-Feng Chiu, Jonathan Bachrach, Brian Zimmer, Milovan Blagojevic, Rimas Avizienis
Publikováno v:
IEEE Micro. 36:8-20
The final phase of CMOS technology scaling provides continued increases in already vast transistor counts, but only minimal improvements in energy efficiency, thus requiring innovation in circuits and architectures. However, even huge teams are strug
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66511acfa01e28eb38c8ca3bae16bd9f
https://doi.org/10.1109/mm.2016.11
https://doi.org/10.1109/mm.2016.11
Autor:
Martin Cochet, Krste Asanovic, Borivoje Nikolic, Pi-Feng Chiu, Ben Keller, Elad Alon, Jaehwa Kwak, Colin Schmidt, Palmer Dabbelt, Alberto Puggelli, Brian Zimmer, Milovan Blagojevic, Stevo Bailey, Yunsup Lee
Publikováno v:
ESSCIRC
This work presents a RISC-V system-on-chip (SoC) with integrated voltage regulation and power management implemented in 28nm FD-SOI. A fully integrated switched-capacitor DC-DC converter, coupled with an adaptive clocking system, achieves 82–89% sy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8e148250c08bb9c87f994ca4528ba7ce
https://doi.org/10.1109/esscirc.2016.7598294
https://doi.org/10.1109/esscirc.2016.7598294
Autor:
Jaehwa Kwak, Borivoje Nikolic
Publikováno v:
A-SSCC
A self-adjustable clock generator that closely tracks the voltage dependence of the critical path delay in a microprocessor is presented. Real-time frequency modulation performed by a tunable replica circuit (TRC) reduces the response time to a singl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c9546efea3a6b74bc249707098b3adc
https://doi.org/10.1109/asscc.2015.7387471
https://doi.org/10.1109/asscc.2015.7387471
Autor:
Krste Asanovic, Borivoje Nikolic, Rimas Avizienis, Ruzica Jevtic, Elad Alon, Pi-Feng Chiu, Andrew Waterman, Jaehwa Kwak, Henry Cook, Ben Keller, Brian Richards, Alberto Puggelli, Brian Zimmer, Milovan Blagojevic, Yunsup Lee, Stevo Bailey
Publikováno v:
Hot Chips Symposium
This article consists of a collection of slides from the authors' conference presentation. The topics discussed included: Motivation/Raven Project Goals; On-Chip Switched Capacitor DC-DC Converters; Raven3 Chip Architecture; Raven3 Implementation; Ra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01fb37fee72be67793ed981c7eaf1fa1
https://doi.org/10.1109/hotchips.2015.7477469
https://doi.org/10.1109/hotchips.2015.7477469
Autor:
Hanh-Phuc Le, Po-Hung Chen, Rimas Avizienis, Pi-Feng Chiu, Stevo Bailey, Krste Asanovic, Brian Richards, Ben Keller, Ruzica Jevtic, Brian Zimmer, Borivoje Nikolic, Nicholas Sutardja, Elad Alon, Yunsup Lee, Milovan Blagojevic, Jaehwa Kwak, Andrew Waterman, Alberto Puggelli, Philippe Flatresse
Publikováno v:
VLSIC
This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using on
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20d279110d52ce2eff44f8000156df88
https://doi.org/10.1109/vlsic.2015.7231305
https://doi.org/10.1109/vlsic.2015.7231305