Zobrazeno 1 - 10
of 93
pro vyhledávání: '"Jae-Whui Kim"'
Autor:
Jun-Hyun Bae, Yong-Sang You, Jae-Yoon Sim, Hong-June Park, Young-Chan Jang, Ho-Young Lee, Jae-Whui Kim
Publikováno v:
JSTS:Journal of Semiconductor Technology and Science. 8:318-325
A 1.2 V 7-bit 1 GS/s CMOS flash ADC with an interpolation factor of 4 is implemented by using a 0.13 ㎛ CMOS process. A digital calibration of DC reference voltage is proposed for the 1 st preamp array to compensate for the input offset voltage of d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::136a68edce44c07c1ce248c1798be89b
https://doi.org/10.5573/jsts.2008.8.4.318
https://doi.org/10.5573/jsts.2008.8.4.318
Autor:
Un-Ku Moon, Min Gyu Kim, Seung-Bin You, Gabor C. Temes, Pavan Kumar Hanumolu, Sang-Ho Kim, Sang-Hyeon Lee, Gil-Cho Ahn, Jae-Whui Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:1195-1206
A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5cf05fcfaf9d9633dbb3d9e881e6fd75
https://doi.org/10.1109/jssc.2008.920329
https://doi.org/10.1109/jssc.2008.920329
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 54:601-605
A slew-rate-controlled output driver having a constant transition time irrespective of environmental variations is described in this brief. The proposed output driver employs a capacitive feedback between the output and input of the driver to allow i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0262bd5c402e31280aeee6942659658a
https://doi.org/10.1109/tcsii.2007.895314
https://doi.org/10.1109/tcsii.2007.895314
Autor:
Jae-Whui Kim, Sang-Ho Kim, Gabor C. Temes, Un-Ku Moon, Seung-Bin You, Ruopeng Wang, Sang-Hyeon Lee
Publikováno v:
Analog Integrated Circuits and Signal Processing. 51:27-31
An oversampled digital-to-analog converter (DAC) with a 100-dB A-weighted dynamic range is presented. It uses a switched-capacitor (SC) array to transfer the sampled charges directly into the headphone driver. The overall DAC gain is precisely contro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f7f2e8d244a54bf67caeca7f02da9d33
https://doi.org/10.1007/s10470-007-9033-0
https://doi.org/10.1007/s10470-007-9033-0
Publikováno v:
IEEE Journal of Solid-State Circuits. 38:1227-1233
A slew-rate controlled output driver adopting the delay compensation method has been implemented using 0.18-/spl mu/m CMOS process for storage device interface. A phase-locked loop (PLL) is used to generate compensation current and constant delay tim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d48f5bf5c9dc592cd30c7de5e248603
https://doi.org/10.1109/jssc.2003.813253
https://doi.org/10.1109/jssc.2003.813253
Publikováno v:
IEEE Transactions on Consumer Electronics. 43:863-867
In a front-end receiver of DBS (direct broadcasting for satellite), the A/D converter, which converts I/Q signals of the QPSK demodulator into the digital domain, has an important role in determining the system performance. A 3 V dual A/D converter w
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::04eb18e94d3c7b427842ff1dcf4b4a58
https://doi.org/10.1109/30.628744
https://doi.org/10.1109/30.628744
Autor:
Sung-No Lee, Jae-Whui Kim, Ho-Jin Park, Un-Ku Moon, Sang-Ho Kim, Seung-Bin You, Pavan Kumar Hanumolu, Sunwoo Kwon
Publikováno v:
CICC
A multi-bit third-order hybrid ΔΣ ADC is presented. The ADC obviates the need for dynamic element matching (DEM) in the critical feedback path, eliminating the systematic boundary of high clock frequency. This implementation incorporates continuous
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4e5ad94f321d0ea81a15c4eded80e9eb
https://doi.org/10.1109/cicc.2009.5280871
https://doi.org/10.1109/cicc.2009.5280871
Autor:
Hae-Seung Lee, Sung-No Lee, Jae-Whui Kim, Wang-Seup Yeum, Ho-Jin Park, Moo-Yeol Choi, Seung-Bin You
Publikováno v:
CICC
A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65 nm CMOS process, dissipates 15 mW and occupies an active die area of 0.28 mm2. A post integration time control (PITC) technique is proposed for calibratio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2ca2f78dfe5f1f61e32646c1d68b6792
https://doi.org/10.1109/cicc.2008.4672028
https://doi.org/10.1109/cicc.2008.4672028
Autor:
Kyoung-Ho Moon, Hae-Seung Lee, Taehwan Oh, Ho-Young Lee, Jae-Whui Kim, Ju-Hwa Kim, Ho-Jin Park
Publikováno v:
CICC
Time constant control (TCC) incorporating on-chip digital self-calibration technique performs two-step calibration of pipeline ADC stage errors and reduces power consumption at the same time. Using the proposed technique, the current of the amplifier
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f888ea0609bbc2f6f798d66b6a045f7
https://doi.org/10.1109/cicc.2008.4672033
https://doi.org/10.1109/cicc.2008.4672033
Autor:
Seung-Hee Yang, Jae-Whui Kim, Hyun-goo Kim, Jongshin Shin, Jiyoung Kim, Jongjae Ryu, Bongjin Kim, Chi-Won Kim, Jae-Hyun Park
Publikováno v:
CICC
A 65 nm HDMI TX PHY was designed with supply-regulated dual-tuning PLL and blending multiplexer. The proposed PLL uses a new dual-tuning scheme for small capacitor and low-jitter while keeping the supply regulation capability. A fractional-N operatio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c544855bee2fd6de84c93943bac4fa0d
https://doi.org/10.1109/cicc.2008.4672067
https://doi.org/10.1109/cicc.2008.4672067