Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Jack Kenney"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:685-695
This paper presents a sub-baud-rate clock and data recovery (CDR) circuit that can recover clock and data using only differential quarter-rate clocks. A combination of eight samplers and an integrator recover four data bits in each clock cycle. Four
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aaaee359cdb73bd6609727e8faefe9ac
https://doi.org/10.1109/jssc.2018.2885540
https://doi.org/10.1109/jssc.2018.2885540
Publikováno v:
Journal of Constructional Steel Research. 165:105839
Steel structures with fracture-critical components and connections rightly require quality control to help prevent catastrophic failure. Specifically, fracture-critical welded connections require evidence of brittle fracture capacity, which can take
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::913d2e52416d15e36999462b88070496
https://doi.org/10.1016/j.jcsr.2019.105839
https://doi.org/10.1016/j.jcsr.2019.105839
Publikováno v:
ESSCIRC
A reference-less clock and data recovery unit (CDR) for non-retiming analog crosspoint switch applications is presented. The CDR supports an eye-opening monitor (EOM) utility that facilitates adaptive equalization and is shared among all lanes, amort
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b1b5e9cec692cf3aa089f0b7c76fb18d
https://doi.org/10.1109/esscirc.2018.8494296
https://doi.org/10.1109/esscirc.2018.8494296
Publikováno v:
CICC
A sub-baud-rate CDR that can recover clock and data using only a quarter-rate clock is presented. Four data bits are recovered in each clock cycle using eight samplers and a current integrator. Four of the eight samplers used for data recovery are re
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5ba82295c47ce345e4fd6db0ff791363
https://doi.org/10.1109/cicc.2018.8357078
https://doi.org/10.1109/cicc.2018.8357078
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:2859-2864
This special issue of the IEEE Journal of Solid-State Circuits is dedicated to the papers taken from the best of the Data Converters, RF, Analog,Wireless Communications, andWireline Communications sessions at the IEEE International Solid-State Circui
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f666f0f4e5a7cfc8a3d4665b097d6ab
https://doi.org/10.1109/jssc.2012.2219253
https://doi.org/10.1109/jssc.2012.2219253
Autor:
Jack Kenney, Frank O'Mahony
Publikováno v:
ISSCC
In your current job, would you describe yourself as a "Brilliant Technology Innovator" or "Indentured Spice Monkey"? In the competitive and fast-paced semiconductor industry, most jobs require people to do at least a little (but more often a lot) of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::53b07f159ae9e7b4f48c39fbe03aa6a3
https://doi.org/10.1109/isscc.2015.7063152
https://doi.org/10.1109/isscc.2015.7063152
Autor:
M.H. Eskiyerli, Sivanendra Selvanayagam, Jack Kenney, Eric Evans, Declan M. Dalton, B. Hilton, T. Kwok, Lawrence M. Devito, D. Hitchcox, V. Reddy, C. McQuilkin, P. Shepherd, Ward S. Titus, D. Mulcahy
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:2901-2910
A 9.95-11.3-Gb/s transceiver in 0.13-mum CMOS for XFP modules is presented. The CDR uses a dual-loop DLL/PLL with a binary phase detector to exceed XFP jitter specifications. The dual loop solves the problem of having a controlled jitter transfer ban
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a64ef4857e3a864b7a8699297786a8c6
https://doi.org/10.1109/jssc.2006.884344
https://doi.org/10.1109/jssc.2006.884344
Autor:
Todd Weigandt, Ward S. Titus, Stuart McCracken, Richard Soenneker, Terry Chen, Larry DeVito, Jack Kenney, Declan M. Dalton
Publikováno v:
CICC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::928175f17ca4a886e5651fc11225fd10
https://doi.org/10.1109/cicc.2014.6946023
https://doi.org/10.1109/cicc.2014.6946023
Autor:
Jack Kenney
Publikováno v:
IEEE Solid-State Circuits Magazine. 7:69-70
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c5d68a8b8cc7a1018a02f9d87ab6400
https://doi.org/10.1109/mssc.2015.2418473
https://doi.org/10.1109/mssc.2015.2418473
Publikováno v:
2007 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.
An LC tank providing clock buffering for a half-rate binary phase detector in a clock and data recovery circuit is described. This paper analyzes the trade-offs involved in choosing the Q of the LC tank, presents an automatic tuning method for the LC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9842ffbad6a2328d05acaf0de78252b6
https://doi.org/10.1109/rfic.2007.380937
https://doi.org/10.1109/rfic.2007.380937