Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Jack Hwang"'
Autor:
M. Diebel, Jack Hwang, A. Budrevich, M. Liu, Martin D. Giles, S. Govindaraju, Patrick H. Keys, Harold W. Kennel
Publikováno v:
2006 14th IEEE International Conference on Advanced Thermal Processing of Semiconductors.
Forming highly active shallow junctions is a key component enabling low external resistance and high transistor performance. Millisecond flash or scanning laser anneals can be used to contain diffusion and optimize activation, either directly by leve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cfe6a678d85f6f1ebaedb37a90847f37
https://doi.org/10.1109/rtp.2006.367986
https://doi.org/10.1109/rtp.2006.367986
Autor:
Bruce Woolery, Swaminathan Sivakumar, C. Kenyon, Ramune Nagisetty, M. Bost, Cory E. Weber, P. Bai, Jack Hwang, T. Marieb, C. Auth, Kevin Zhang, Andrew Ott, Yeoh Andrew W, Sridhar Balakrishnan, D. Ingerly, C. Parker, J. Sebastian, Ruth A. Brain, Makarem A. Hussein, J. Neirynck, Anand Portland Murthy, Z. Ma, Seung Hwan Lee, Nick Lindert, Joseph M. Steigerwald, E. Lee, Mark Y. Liu, R. Shaheed, M. Bohr, R. Heussner, J. Jeong, V. Chikarmane, Sanjay Natarajan, R. James, S. Tyagi
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ac646c890427393477aae9a64374b642
https://doi.org/10.1109/iedm.2004.1419253
https://doi.org/10.1109/iedm.2004.1419253
Autor:
Jack Hwang, S. Corcoran, Patrick H. Keys, J. Sandford, S. Cea, Martin D. Giles, Harold W. Kennel, A. D. Lilak
Publikováno v:
Digest. International Electron Devices Meeting.
This paper presents an integrated modeling approach to address diffusion and activation challenges in sub-90 nm CMOS technology. Co-implants of F and Ge are shown to reduce diffusion rates and a new model for the interactive effects is presented. Com
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::464cc30fcf62c3ea0fddff22602cc0a0
https://doi.org/10.1109/iedm.2002.1175976
https://doi.org/10.1109/iedm.2002.1175976
Autor:
Martin Giles, Patrick H. Keys, Stephan Cea, M. Stettler, Cory E. Weber, Lucian Shifren, Karson L. Knutson, Jack Hwang, Paul Portland Davids, Roza Kotlyar, Suddha Talukdar
Publikováno v:
ECS Meeting Abstracts. :625-625
Design for Manufacturability (DFM) is a phrase that often accompanies discussion of layout optimization for lithography process effects, particularly Optical Proximity Correction (OPC). In an environment where process technology and circuit design ar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::570c0d6debf584f6b043fc761da72724
https://doi.org/10.1149/ma2008-01/16/625
https://doi.org/10.1149/ma2008-01/16/625
Publikováno v:
Spectrochimica Acta Part B: Atomic Spectroscopy. 38:165-174
The spectroscopic determination of rare earth elements (REE's) in geological matrices is generally complicated by the relatively low concentrations of these elements, the high concentrations or matrix elements and their interferences in the analyte d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ec72b8c87216e253f089b37db70bc9c
https://doi.org/10.1016/0584-8547(83)80113-x
https://doi.org/10.1016/0584-8547(83)80113-x